tharunchitipolu / Multi-operations-toolbox-with-baugh-wooley-multiplier Star 9 Code Issues Pull requests Given A and B are 64-bit inputs. With two selection lines s1 and s0 to perform the operations, A+B, A-B, AB, C+AB using Baugh Wooley multiplier digital verilog vlsi verilog-hdl multiplier hardware-description-language vlsi-circuits baugh-wooley digitalelectronics Updated Jun 1, 2021 Verilog
MohammadNiknam17 / Signed-4BIT-Binary-Multiplier_VHDL-FPGA Star 3 Code Issues Pull requests These are VHDL codes for a signed 4bit multiplier using 4bit adders. Base on Baugh-Wooley Method. fpga binary vhdl signed fulladder 4bit multiplier halfadder vhdl-code full-adder baugh-wooley Updated May 10, 2021 VHDL