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verilator Public
Forked from verilator/verilatorVerilator open-source SystemVerilog simulator and lint system
C++ GNU Lesser General Public License v3.0 UpdatedMar 10, 2025 -
solutions to exercises from the book "Logic Design and Verification Using SystemVerilog" by Donald Thomas
SystemVerilog UpdatedFeb 23, 2025 -
opentitan Public
Forked from lowRISC/opentitanOpenTitan: Open source silicon root of trust
SystemVerilog Apache License 2.0 UpdatedFeb 19, 2025 -
verible Public
Forked from chipsalliance/veribleVerible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
C++ Other UpdatedFeb 17, 2025 -
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step-motor-controller Public
FPGA project to create a step motor controller
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