Add debug output

semify-eda · Sep 19, 2023 · 3d3ea08 · 3d3ea08
1 parent 01a22ba
commit 3d3ea08
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Showing 3 changed files with 118 additions and 9 deletions.
diff --git a/Makefile b/Makefile
@@ -8,9 +8,9 @@ obj = ${subst $(SRCDIR),$(OBJDIR),$(addsuffix .o, $(basename $(csrc)))}
 $(info $(csrc))
 $(info $(obj))
 
-default: fstdumper.so
+all: fstdumper.so
 
-CFLAGS = -I $(SRCDIR)/config -fPIC -O2
+CFLAGS = -I $(SRCDIR)/config -fPIC -O2 -DDEBUG
 LDFLAGS = -lz -shared
 
 TESTBENCH = $(wildcard testbench/*.sv)
@@ -49,7 +49,7 @@ simulation-vcs: fstdumper.so
  vcs -sverilog -full64 +vpi -load ./fstdumper.so -debug_acc+pp+f+dmptf $(TESTBENCH)
  ./simv
 
-.PHONY: clean
+.PHONY: clean all simulation-iverilog simulation-xrun simulation-vsim
 clean:
  rm -f $(obj) *.so *.so.vpi *.vvp *.fst
 
diff --git a/src/debug.h b/src/debug.h
@@ -0,0 +1,11 @@
+#ifndef DEBUG_H
+#define DEBUG_H
+
+#ifndef DEBUG
+#define DEBUG 0
+#endif
+
+#define debug_print(...) \
+ do { if (DEBUG) { fprintf(stderr, "%s(%d) : ", __FILE__, __LINE__); fprintf(stderr, __VA_ARGS__); } } while (0)
+
+#endif