masking-ise: Work on finite field instructions.

- See #33

- Integrate instructions into decoder and operand selection.

- Operations are routed to the masking ALU correctly.

- Currently the masking ALU just executes the instructions as a nop.

- Unit tests written, but expected result needs calculating.

Still to do:

- Formal checker.

- Expected result for the unit test.

- Masking ALU instruction implementation.

 On branch scarv/xcrypto/masking-ise
 Your branch is up-to-date with 'origin/scarv/xcrypto/masking-ise'.

 Changes to be committed:
	modified:   docs/masking-ise.md
	modified:   flow/gtkwave/verilator.gtkw
	modified:   rtl/core/frv_common.vh
	modified:   rtl/core/frv_masked_alu.v
	modified:   rtl/core/frv_pipeline_decode.v
	modified:   rtl/core/frv_pipeline_decode.vh
	modified:   rtl/core/frv_pipeline_execute.v
	modified:   verif/unit/masking-ise/masked-instrs.S
	modified:   verif/unit/masking-ise/masking-ise.c

docs/masking-ise.md

@@ -103,6 +103,8 @@ Instruction     | Operand A | Operand B | Operand C | Operand D
 `mask_b_slli`   | `rs1.lo`  | shamt     | `rs1.hi`  |         
 `mask_b_srli`   | `rs1.lo`  | shamt     | `rs1.hi`  |         
 `mask_b_rori`   | `rs1.lo`  | shamt     | `rs1.hi`  |         
+`mask_f_mul`    | `rs1.lo`  | `rs2.lo`  | `rs1.hi`  | `rs2.hi`
+`mask_f_aff`    | `rs1.lo`  |           | `rs1.hi`  |         
 
 
 ## Example Masked ALU interface transactions

flow/gtkwave/verilator.gtkw

@@ -1,15 +1,15 @@
 [*]
 [*] GTKWave Analyzer v3.3.86 (w)1999-2017 BSI
-[*] Fri Jun  5 08:29:26 2020
+[*] Thu Jul 30 11:21:22 2020
 [*]
-[dumpfile] "/home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/speck/speck.vcd"
-[dumpfile_mtime] "Fri Jun  5 08:23:54 2020"
-[dumpfile_size] 47462264
+[dumpfile] "/home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/masking-ise/masking-ise.vcd"
+[dumpfile_mtime] "Thu Jul 30 11:17:48 2020"
+[dumpfile_size] 30747039
 [savefile] "/home/work/scarv/scarv-soc/extern/scarv-cpu/flow/gtkwave/verilator.gtkw"
-[timestart] 123054
+[timestart] 17241
 [size] 1920 1025
 [pos] -1 -1
-*-6.750972 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+*-7.925536 17806 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
 [treeopen] TOP.
 [treeopen] TOP.frv_core.
 [treeopen] TOP.frv_core.i_pipeline.
@@ -18,7 +18,7 @@
 [treeopen] TOP.frv_core.i_pipeline.i_pipeline_s1_decode.
 [treeopen] TOP.frv_core.i_pipeline.i_pipeline_s1_decode.i_decode_pipereg.
 [treeopen] TOP.frv_core.i_pipeline.i_pipeline_s2_execute.
-[treeopen] TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.
+[treeopen] TOP.frv_core.i_pipeline.i_pipeline_s2_execute.masking_ise_implemented.
 [sst_width] 340
 [signals_width] 504
 [sst_expanded] 1
@@ -97,7 +97,7 @@ TOP.frv_core.i_pipeline.dmem_error
 @800200
 -Trace
 @2022
-^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/sparx/sparx.gtkwl
+^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/masking-ise/masking-ise.gtkwl
 TOP.frv_core.trs_instr[31:0]
 @22
 TOP.frv_core.trs_instr[31:0]
@@ -258,18 +258,18 @@ TOP.frv_core.i_pipeline.s1_rs2_rdatahi[31:0]
 @1401200
 -RS2
 -Forwarding
-@c00201
+@c00200
 -Pipeline Tracing
 @2022
-^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/sparx/sparx.gtkwl
+^3 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/sparx/sparx.gtkwl
 TOP.frv_core.i_pipeline.i_pipeline_s1_decode.n_s2_instr[31:0]
 @22
 TOP.frv_core.i_pipeline.i_pipeline_s1_decode.n_s2_opr_a[31:0]
 TOP.frv_core.i_pipeline.i_pipeline_s1_decode.n_s2_opr_b[31:0]
 TOP.frv_core.i_pipeline.i_pipeline_s1_decode.n_s2_opr_c[31:0]
 TOP.frv_core.i_pipeline.i_pipeline_s1_decode.n_s2_opr_d[31:0]
 @2022
-^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/sparx/sparx.gtkwl
+^3 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/sparx/sparx.gtkwl
 TOP.frv_core.i_pipeline.s2_instr[31:0]
 @22
 TOP.frv_core.i_pipeline.s2_opr_a[31:0]
@@ -280,15 +280,15 @@ TOP.frv_core.i_pipeline.s2_opr_d[31:0]
 TOP.frv_core.i_pipeline.i_pipeline_s1_decode.s2_opr_c_rev
 TOP.frv_core.i_pipeline.i_pipeline_s1_decode.s2_opr_d_rev
 @2022
-^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/sparx/sparx.gtkwl
+^3 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/sparx/sparx.gtkwl
 TOP.frv_core.i_pipeline.s3_instr[31:0]
 @22
 TOP.frv_core.i_pipeline.s3_opr_a[31:0]
 TOP.frv_core.i_pipeline.s3_opr_b[31:0]
 @28
 TOP.frv_core.i_pipeline.s3_opr_b_rev
 @2022
-^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/sparx/sparx.gtkwl
+^3 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/sparx/sparx.gtkwl
 TOP.frv_core.i_pipeline.s4_instr[31:0]
 @22
 TOP.frv_core.i_pipeline.s4_opr_a[31:0]
@@ -297,7 +297,7 @@ TOP.frv_core.i_pipeline.s4_opr_b[31:0]
 TOP.frv_core.i_pipeline.s4_opr_b_rev
 @22
 TOP.frv_core.i_pipeline.i_gprs.gprs_odd_rev[15:0]
-@1401201
+@1401200
 -Pipeline Tracing
 @c00200
 -Pipe - S1 Decode
@@ -330,7 +330,7 @@ TOP.frv_core.i_pipeline.i_pipeline_s1_decode.oprd_ld_en
 @22
 TOP.frv_core.i_pipeline.s1_data[31:0]
 @2022
-^3 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/masking-ise/masking-ise.gtkwl
+^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/masking-ise/masking-ise.gtkwl
 TOP.frv_core.i_pipeline.i_pipeline_s1_decode.n_s2_instr[31:0]
 @28
 TOP.frv_core.i_pipeline.i_pipeline_s1_decode.s1_bubble
@@ -374,13 +374,13 @@ TOP.frv_core.i_pipeline.i_pipeline_s1_decode.i_frv_leak.leak_prng[31:0]
 @1401200
 -Leakage Instructions
 -Pipe - S1 Decode
-@c00200
+@800200
 -Pipe - S2 Execute
 @28
 TOP.frv_core.i_pipeline.s2_busy
 TOP.frv_core.i_pipeline.s2_valid
 @2022
-^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/sparx/sparx.gtkwl
+^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/masking-ise/masking-ise.gtkwl
 TOP.frv_core.i_pipeline.s2_instr[31:0]
 @c00022
 TOP.frv_core.i_pipeline.s2_instr[31:0]
@@ -471,27 +471,9 @@ TOP.frv_core.i_pipeline.s2_uop[4:0]
 @800200
 -Masked ALU
 @28
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.g_clk
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.g_resetn
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.valid
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.ready
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.flush
-@200
--
-@28
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.op_b2a
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.op_b_add
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.op_b_mask
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.op_b_rori
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.op_b_xor
-@22
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.rs1_s0[31:0]
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.rs1_s1[31:0]
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.rs2_s0[31:0]
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.rs2_s1[31:0]
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.rd_s0[31:0]
-TOP.frv_core.i_pipeline.i_pipeline_s2_execute.i_frv_masked_alu.rd_s1[31:0]
-@200
+TOP.frv_core.i_pipeline.i_pipeline_s2_execute.masking_ise_implemented.i_frv_masked_alu.valid
+TOP.frv_core.i_pipeline.i_pipeline_s2_execute.masking_ise_implemented.i_frv_masked_alu.ready
+@201
 -
 @22
 TOP.frv_core.i_pipeline.i_pipeline_s2_execute.n_s3_opr_a[31:0]
@@ -525,13 +507,14 @@ TOP.frv_core.i_pipeline.i_pipeline_s2_execute.alu_ready
 TOP.frv_core.i_pipeline.i_pipeline_s2_execute.alu_valid
 @1401200
 -ALI
+@1000200
 -Pipe - S2 Execute
 @800200
 -Pipe - S3 Memory
 @28
 TOP.frv_core.i_pipeline.s3_busy
 @2022
-^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/sparx/sparx.gtkwl
+^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/masking-ise/masking-ise.gtkwl
 TOP.frv_core.i_pipeline.s3_instr[31:0]
 @22
 TOP.frv_core.i_pipeline.s3_instr[31:0]
@@ -612,7 +595,7 @@ TOP.frv_core.i_pipeline.s4_flush
 @22
 TOP.frv_core.i_pipeline.s4_instr[31:0]
 @2022
-^3 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/masking-ise/masking-ise.gtkwl
+^1 /home/work/scarv/scarv-soc/extern/scarv-cpu/work/unit/masking-ise/masking-ise.gtkwl
 TOP.frv_core.i_pipeline.s4_instr[31:0]
 @22
 TOP.frv_core.i_pipeline.s4_opr_a[31:0]

rtl/core/frv_common.vh

@@ -112,6 +112,8 @@ localparam MSK_B_SUB    = {2'b00, 3'b110};
 localparam MSK_B_SLLI   = {2'b01, 3'b001};
 localparam MSK_B_SRLI   = {2'b01, 3'b010};
 localparam MSK_B_RORI   = {2'b01, 3'b100};
+localparam MSK_F_MUL    = {2'b01, 3'b101};
+localparam MSK_F_AFF    = {2'b01, 3'b110};
 
 localparam CSR_READ     = 4;
 localparam CSR_WRITE    = 3;

rtl/core/frv_masked_alu.v

@@ -63,6 +63,8 @@ input  wire        op_b_sub         , // Binary masked subtraction
 input  wire        op_b_srli        , // Shift right, shamt in msk_rs2_s0
 input  wire        op_b_slli        , // Shift left, shamt in msk_rs2_s0
 input  wire        op_b_rori        , // Shift right, shamt in msk_rs2_s0
+input  wire        op_f_mul         , // Finite field multiply
+input  wire        op_f_aff         , // Affine transform
 
 input  wire        prng_update      , // Force the PRNG to update.
 
@@ -351,7 +353,11 @@ assign rd_s1 = {XLEN{op_b_not}} &  (n_prng ^ mnot1) |
                {XLEN{op_b2a  }} &  mb2a1 |
                {XLEN{op_msk  }} &  rmask1;
 
-assign ready = mnot_rdy || (dologic && mlogic_rdy) || madd_rdy || shr_rdy || msk_rdy ;
+wire    temp_mask_f_ready = op_f_mul || op_f_aff;
+
+assign ready = mnot_rdy || (dologic && mlogic_rdy) ||
+              madd_rdy || shr_rdy || msk_rdy       ||
+              temp_mask_f_ready;
 assign mask  = prng;
 
 endmodule

rtl/core/frv_pipeline_decode.v

@@ -209,7 +209,8 @@ assign n_s2_fu[P_FU_MSK] =
     dec_mask_a_remask || dec_mask_b_not     ||
     dec_mask_b_and     || dec_mask_b_ior    || dec_mask_b_xor     ||
     dec_mask_b_add     || dec_mask_b_sub    || dec_mask_b_slli    ||
-    dec_mask_b_srli    || dec_mask_b_rori;
+    dec_mask_b_srli    || dec_mask_b_rori   ||
+    dec_mask_f_mul     || dec_mask_f_aff    ;
 
 //
 // Encoding field extraction
@@ -458,7 +459,9 @@ wire [OP:0] uop_msk =
     {1+OP{dec_mask_b_sub      }} & MSK_B_SUB        |
     {1+OP{dec_mask_b_srli     }} & MSK_B_SRLI       |
     {1+OP{dec_mask_b_slli     }} & MSK_B_SLLI       |
-    {1+OP{dec_mask_b_rori     }} & MSK_B_RORI       ;
+    {1+OP{dec_mask_b_rori     }} & MSK_B_RORI       |
+    {1+OP{dec_mask_f_mul      }} & MSK_F_MUL        |
+    {1+OP{dec_mask_f_aff      }} & MSK_F_AFF        ;
 
 assign n_s2_uop =
     uop_alu |
@@ -797,7 +800,7 @@ assign n_s2_opr_src[DIS_OPRB_RS2 ] = // Operand B sources RS2
     dec_xc_gather_b      || dec_xc_scatter_b     || dec_xc_gather_h      ||
     dec_xc_scatter_h     ||
     dec_mask_b_not || dec_mask_b_and || dec_mask_b_ior || dec_mask_b_xor ||
-    dec_mask_b_add || dec_mask_b_sub ;
+    dec_mask_b_add || dec_mask_b_sub || dec_mask_f_mul ;
 
 assign n_s2_opr_src[DIS_OPRB_IMM ] = // Operand B sources immediate
     dec_addi       || dec_c_addi     || dec_andi       || dec_c_andi     ||
@@ -835,7 +838,8 @@ wire oprc_src_rs1_hi =
     dec_mask_b_remask   || dec_mask_a_remask   ||
     dec_mask_b_not      || dec_mask_b_and      || dec_mask_b_ior      ||
     dec_mask_b_xor      || dec_mask_b_add      || dec_mask_b_sub      ||
-    dec_mask_b_slli     || dec_mask_b_srli     || dec_mask_b_rori     ;
+    dec_mask_b_slli     || dec_mask_b_srli     || dec_mask_b_rori     ||
+    dec_mask_f_mul      || dec_mask_f_aff      ;
 
 assign n_s2_opr_src[DIS_OPRC_RS3 ] = // Operand C sources RS3
     dec_xc_str_b   || dec_xc_str_h   || dec_xc_str_w   || dec_xc_mmul_3  ||
@@ -858,7 +862,8 @@ assign n_s2_opr_src[DIS_OPRC_PCIM] = // Operand C sources PC+immediate
 // Operand D sources rs2 high half of double-width read
 wire oprd_src_rs2_hi = 
     dec_mask_b_not      || dec_mask_b_and      || dec_mask_b_ior      ||
-    dec_mask_b_xor      || dec_mask_b_add      || dec_mask_b_sub      ;
+    dec_mask_b_xor      || dec_mask_b_add      || dec_mask_b_sub      ||
+    dec_mask_f_mul      ;
 
 //
 // Trap catching

rtl/core/frv_pipeline_decode.vh

@@ -162,9 +162,11 @@ wire dec_mask_b_ior     = XC_CLASS_MASK && (d_data & 32'hfe10f0ff) == 32'h200605
 wire dec_mask_b_xor     = XC_CLASS_MASK && (d_data & 32'hfe10f0ff) == 32'h200405b;
 wire dec_mask_b_add     = XC_CLASS_MASK && (d_data & 32'hfe10f0ff) == 32'h200005b;
 wire dec_mask_b_sub     = XC_CLASS_MASK && (d_data & 32'hfe10f0ff) == 32'h200105b;
-wire dec_mask_b_slli = XC_CLASS_MASK && (d_data & 32'hfc00f0ff) == 32'h800005b;
-wire dec_mask_b_srli = XC_CLASS_MASK && (d_data & 32'hfc00f0ff) == 32'h800105b;
-wire dec_mask_b_rori = XC_CLASS_MASK && (d_data & 32'hfc00f0ff) == 32'h800205b;
+wire dec_mask_b_slli    = XC_CLASS_MASK && (d_data & 32'hfc00f0ff) == 32'h800005b;
+wire dec_mask_b_srli    = XC_CLASS_MASK && (d_data & 32'hfc00f0ff) == 32'h800105b;
+wire dec_mask_b_rori    = XC_CLASS_MASK && (d_data & 32'hfc00f0ff) == 32'h800205b;
+wire dec_mask_f_mul     = XC_CLASS_MASK && (d_data & 32'hfe10f0ff) == 32'h600005b;
+wire dec_mask_f_aff     = XC_CLASS_MASK && (d_data & 32'hfff0f0ff) == 32'h600205b;
 
 
 wire invalid_instr = !(dec_lui       ||dec_auipc     ||dec_jal
@@ -209,5 +211,6 @@ dec_mask_b_unmask  || dec_mask_b_remask  || dec_mask_a_mask    ||
 dec_mask_a_unmask  || dec_mask_a_remask  || dec_mask_b_not     ||
 dec_mask_b_and     || dec_mask_b_ior     || dec_mask_b_xor     ||
 dec_mask_b_add     || dec_mask_b_sub     || dec_mask_b_slli    ||
-dec_mask_b_srli    || dec_mask_b_rori
+dec_mask_b_srli    || dec_mask_b_rori    ||
+dec_mask_f_mul     || dec_mask_f_aff
 );

rtl/core/frv_pipeline_execute.v

@@ -303,6 +303,8 @@ wire        msk_op_b_sub    = XC_CLASS_MASK && s2_uop == MSK_B_SUB   ;
 wire        msk_op_b_srli   = XC_CLASS_MASK && s2_uop == MSK_B_SRLI  ;
 wire        msk_op_b_slli   = XC_CLASS_MASK && s2_uop == MSK_B_SLLI  ;
 wire        msk_op_b_rori   = XC_CLASS_MASK && s2_uop == MSK_B_RORI  ;
+wire        msk_op_f_mul    = XC_CLASS_MASK && s2_uop == MSK_F_MUL   ;
+wire        msk_op_f_aff    = XC_CLASS_MASK && s2_uop == MSK_F_AFF   ;
 
 wire [XL:0] msk_rs1_s0      = s2_opr_a;
 wire [XL:0] msk_rs1_s1      ;
@@ -568,6 +570,8 @@ frv_masked_alu #(
 .op_b_srli   (msk_op_b_srli   ), // Masked shift right, shamt in msk_rs2_s0
 .op_b_slli   (msk_op_b_slli   ), // Masked shift left, shamt in msk_rs2_s0
 .op_b_rori   (msk_op_b_rori   ), // Masked shift right, shamt in msk_rs2_s0
+.op_f_mul    (msk_op_f_mul    ), // Finite field multiply
+.op_f_aff    (msk_op_f_aff    ), // Affine transform
 .prng_update (msk_prng_update ), // Force the PRNG to update.
 .rs1_s0      (msk_rs1_s0      ), // RS1 Share 0
 .rs1_s1      (msk_rs1_s1      ), // RS1 Share 1

verif/unit/masking-ise/masked-instrs.S

@@ -229,3 +229,29 @@ test_masked_a2b:
     ret
 .endfunc
 
+
+.global test_masked_f_mul
+.func   test_masked_f_mul
+test_masked_f_mul:
+
+    mask.a.mask     (t2,t1), a0
+    mask.a.mask     (t4,t3), a1
+    mask.f.mul      (a1,a0), (t2,t1), (t4,t3)
+    mask.b.unmask    a0    , (a1,a0)
+
+.test_masked_f_mul:
+    ret
+.endfunc
+
+
+.global test_masked_f_aff
+.func   test_masked_f_aff
+test_masked_f_aff:
+
+    mask.b.mask     (t2,t1), a0
+    mask.f.aff      (a1,a0), (t2,t1)
+    mask.b.unmask    a0    , (a1,a0)
+
+.test_masked_f_aff:
+    ret
+.endfunc

verif/unit/masking-ise/masking-ise.c

@@ -15,6 +15,8 @@ extern uint32_t test_masked_brm(uint32_t a);   //boolean remask
 extern uint32_t test_masked_b2a(uint32_t a);
 extern uint32_t test_masked_arm(uint32_t a);   //arithmetic remask
 extern uint32_t test_masked_a2b(uint32_t a);
+extern uint32_t test_masked_f_mul(uint32_t a, uint32_t b);
+extern uint32_t test_masked_f_aff(uint32_t a);
 extern uint32_t test_bit_reverse_representation(uint32_t a, uint32_t b);
 
 void print_result_expectation(
@@ -154,6 +156,24 @@ int test_main() {
         fail = 1;
     }
 
+
+    uint32_t result_f_mul = test_masked_f_mul(lhs,rhs);
+    uint32_t expect_f_mul = result_f_mul; // TODO : Expected result
+    if(result_f_mul != expect_f_mul) {
+        __putstr("test_masked_f_mul [FAIL]\n");
+        print_result_expectation(lhs,rhs,result_f_mul,expect_f_mul);
+        fail = 1;
+    }
+
+
+    uint32_t result_f_aff = test_masked_f_aff(lhs);
+    uint32_t expect_f_aff = result_f_aff; // TODO : Expected result
+    if(result_f_aff != expect_f_aff) {
+        __putstr("test_masked_f_aff [FAIL]\n");
+        print_result_expectation(lhs,rhs,result_f_aff,expect_f_aff);
+        fail = 1;
+    }
+
     return fail;
 
 }