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Add basic jal misalign test #798
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I think it would be nicer just to make the tests pass, but check the negative condition, i.e. install a custom trap handler temporarily, have it record if there was a misaligned exception and return, then uninstall it. |
Yeah we need tests to be able to specify what config to use. I think we'll have to wait until the new config system is available, then we can embed some JSON in them as a comment or something. |
Not opposed to adding more tests, but I would hope this is also covered by any existing riscv-tests or riscv-arch-test? Can we try to run those tests in CI? |
csrwi mtvec, 0 | ||
ret | ||
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.space 1 |
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This doesn't make sense. You can't jump to an odd address. What are you trying to test here exactly?
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Maybe I'm missing something, but isn't that what he wants to test? He wants to cause a misaligned exception
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jal
can never jump to an odd address though. The least significant bit of the offset isn't encoded in the immediate and is always 0. Misaligned exceptions with jal
can only happen when compressed instructions are not supported. Then a jump to a 2 (but not 4) byte aligned word will cause an exception.
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Ok I thought either:
-
He explicitly wants to test if
jal
is correctly implemented by attempting a jump that should generate a trap if the processor correctly enforces alignment requirements, or -
He wants to test a jump to an address with a 2-byte offset when the C extension is not supported. In this case, it should be .space 2 after the misalign: label, not .space 3. (I guess)
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jal can never jump to an odd address though. The least significant bit of the offset isn't encoded in the immediate and is always 0.
I forgot this. 🙏
Ok I thought either:
Both were the original idea.
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In that case, I imagine this test already exists in riscv-tests and/or riscv-arch-test?
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- For riscv-tests: I haven't found anything related to jal and misalign (I don't used riscv-tests much, someone'd better check it again)
- For riscv-arch-test: There are, but I don't know how it checks
mcause
. Does it just assert that the elf run failed?
https://github.com/riscv-non-isa/riscv-arch-test/blob/752c0fb721b9ab264682d491283d98813f95e45b/coverage/cgf.yaml#L422-L430
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Looks like the relevant test in riscv-arch-test is here: https://github.com/riscv-non-isa/riscv-arch-test/blob/752c0fb721b9ab264682d491283d98813f95e45b/riscv-test-suite/rv32i_m/privilege/src/misalign-jal-01.S.
When it traps, the riscv-arch-test trap handler stores all of the relevant CSRs (including mcause) to the signature region of memory, and they are compared to another model (usually Spike).
The cvw-arch-verif tests that are going to be integrated into riscv-arch-test also test misaligned jal: https://github.com/openhwgroup/cvw-arch-verif/blob/f13040a0b752281e3e08f9076d8d164d955a4493/tests/lockstep/priv/ExceptionsM.S#L81
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This test is also in riscv-tests
:
https://github.com/riscv-software-src/riscv-tests/blob/master/isa/rv64si/ma_fetch.S
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Now that we require a compiler for some of the tests (and none of the tests are needed by end users), I wonder if we should switch to using the
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Any opinions on including the vector test suite as a submodule or subtree in the repo (perhaps as an optional test suite)? We had a discussion about it today in the dev partners meeting and I know ACT wants to add it at some point. |
Does it make sense to wait and use it directly from riscv-arch-test once it is integrated if that is the long term plan? |
Seems like a good idea. Technically you can still develop without running the
Ah interesting, any idea what? |
@jordancarlin Yes, I think it makes sense. There is no rush anyway. |
Fully agree with all your statements. I do think CI should compile riscv-tests from source now that we have the infra for it instead of using pre-compiled binaries. While it assumes a fixed ISA, we should be able to support that expected ISA config once the config file support lands. |
That is a good point, but I think the benefits of not storing elfs in the repo and the reduced work to keep up to date with
riscv-arch-test and cvw-arch-verif are likely going to be merging to some degree. The exact details are still being figured out, but at a minimum the privileged tests from cvw-arch-verif are going to migrate to riscv-arch-test, and there are discussions of replacing riscv-ctg and riscv-isac with SystemVerilog coverpoints from cvw-arch-verif as well. If things go down the second route, then many of the unprivileged tests will be updated as well. |
As long as it's still possible to build the model without needing a cross-compiler I don't see any problem. It's easy to gate building and running the tests with a -DENABLE_TESTS=ON/OFF flag that users who only want to build sail as a simulator/for formal proofs/for documentation generation/etc. can set. |
We already have the riscv-tests,first-party test, and we will have riscv-arch-test (based on riscv-admin/dev-partners#38) From my understanding, the relationship between these tests is
If I understand correctly, this PR should be closed now? |
Seems like a similar test is already in both riscv-arch-test and riscv-tests, so no reason to add this as a first-party test. @trdthg are you ok with closing this? |
Of course |
Added a list
tests_fail
to specify which test should fail.Also added two very basic
jal
tests to verify that an error occurs when target address misaligned.