Fix breakpoint.S failing when tcontrol is implemented (#463)

riscv-software-src · Mar 16, 2023 · 0869805 · 0869805
1 parent 654419c
commit 0869805
Showing 1 changed file with 10 additions and 0 deletions.
diff --git a/isa/rv64mi/breakpoint.S b/isa/rv64mi/breakpoint.S
@@ -16,6 +16,16 @@ RVTEST_CODE_BEGIN
   # Set up breakpoint to trap on M-mode fetches.
   li TESTNUM, 2
 
+  # Set tcontrol.mte, otherwise breakpoints are disabled. This may trap,
+  # because tcontrol is an optional register.
+  la a0, 1f
+  csrrw a0, mtvec, a0
+  li a1, 0x8
+  csrs tcontrol, a1
+.p2align 2
+1:
+  csrw mtvec, a0
+
   # Skip tselect if hard-wired.
   csrw tselect, x0
   csrr a1, tselect