Fix envcfg check when S/H-mode is not available

riscv-software-src · Jan 21, 2025 · 5c2dcf3 · 5c2dcf3
1 parent 58da6a2
commit 5c2dcf3
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Showing 2 changed files with 4 additions and 3 deletions.
diff --git a/riscv/csrs.cc b/riscv/csrs.cc
@@ -1846,6 +1846,7 @@ ssp_csr_t::ssp_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask
 void ssp_csr_t::verify_permissions(insn_t insn, bool write) const {
   masked_csr_t::verify_permissions(insn, write);
   DECLARE_XENVCFG_VARS(SSE);
+  auto p = proc; // To match macro usage
   require_envcfg(SSE);
 }
 

diff --git a/riscv/decode_macros.h b/riscv/decode_macros.h
@@ -193,10 +193,10 @@ static inline bool is_aligned(const unsigned val, const unsigned pos)
 #define require_envcfg(field) \
   do { \
     if (((STATE.prv != PRV_M) && (m##field == 0)) || \
-        ((STATE.prv == PRV_U && !STATE.v) && (s##field == 0))) \
+        (p->extension_enabled('S') && (STATE.prv == PRV_U && !STATE.v) && (s##field == 0))) \
       throw trap_illegal_instruction(insn.bits()); \
-    else if (STATE.v && ((h##field == 0) || \
-                        ((STATE.prv == PRV_U) && (s##field == 0)))) \
+    else if (p->extension_enabled('H') && STATE.v && ((h##field == 0) || \
+                        (p->extension_enabled('S') && (STATE.prv == PRV_U) && (s##field == 0)))) \
       throw trap_virtual_instruction(insn.bits()); \
   } while (0);