[ISAC] - Interrupt Coverage Support

.gitignore

@@ -10,8 +10,115 @@
 
 riscv-target/
 
-#ignore venv
-riscv-isac/riscv-env
+# Byte-compiled / optimized / DLL files
+__pycache__/
+*.py[cod]
+*$py.class
+
+# C extensions
+*.so
+
+# Distribution / packaging
+.Python
+env/
+build/
+develop-eggs/
+dist/
+downloads/
+eggs/
+.eggs/
+lib/
+lib64/
+parts/
+sdist/
+var/
+wheels/
+*.egg-info/
+.installed.cfg
+*.egg
+
+# PyInstaller
+#  Usually these files are written by a python script from a template
+#  before PyInstaller builds the exe, so as to inject date/other infos into it.
+*.manifest
+*.spec
+
+# Installer logs
+pip-log.txt
+pip-delete-this-directory.txt
+
+# Unit test / coverage reports
+htmlcov/
+.tox/
+.coverage
+.coverage.*
+.cache
+nosetests.xml
+coverage.xml
+*.cover
+.hypothesis/
+.pytest_cache/
+
+# Translations
+*.mo
+*.pot
+
+# Django stuff:
+*.log
+local_settings.py
+
+# Flask stuff:
+instance/
+.webassets-cache
+
+# Scrapy stuff:
+.scrapy
+
+# Sphinx documentation
+docs/_build/
+
+# PyBuilder
+target/
+
+# Jupyter Notebook
+.ipynb_checkpoints
+
+# pyenv
+.python-version
+
+# celery beat schedule file
+celerybeat-schedule
+
+# SageMath parsed files
+*.sage.py
+
+# dotenv
+.env
+
+# virtualenv
+.venv
+venv/
+ENV/
+
+# Spyder project settings
+.spyderproject
+.spyproject
+
+# Rope project settings
+.ropeproject
+
+# mkdocs documentation
+/site
+
+# mypy
+.mypy_cache/
+
+# IDE settings
+.vscode/
+
+# Coverage Report Files
+*.rpt
+*.html
 
 __pycache__
-riscof_work
+riscof_work

riscv-isac/riscv_isac/InstructionObject.py

@@ -90,7 +90,8 @@ def __init__(
         mem_val =  None,
         trap_dict = None,
         inxFlag = None,
-        is_sgn_extd = None
+        is_sgn_extd = None,
+        mip_updated_val = None
     ):
 
         '''
@@ -135,6 +136,7 @@ def __init__(
         self.matches_for_options = None
         self.mem_val = mem_val
         self.trap_dict = trap_dict
+        self.mip_updated_val = mip_updated_val
 
     def is_sig_update(self):
         return self.instr_name in instrs_sig_update
@@ -198,9 +200,17 @@ def evaluate_instr_vars(self, xlen, flen, arch_state, csr_regfile, instr_vars):
                 instr_vars['access_len'] = 1
         else:
             instr_vars['access_len'] = None
+
         #Update the values for the trap registers
         self.trap_registers_update(instr_vars,self.trap_dict)
 
+        #Update the value of MIP as soon as the hart updates it.
+        if self.mip_updated_val is not None:
+            if isinstance(csr_regfile['mip'], str):
+                csr_regfile['mip'] = int(csr_regfile['mip'], 16) | self.mip_updated_val
+            else:
+                csr_regfile['mip'] = csr_regfile['mip'] | self.mip_updated_val
+
         # capture the register operand values
         rs1_val = self.evaluate_instr_var("rs1_val", instr_vars, arch_state)
         rs2_val = self.evaluate_instr_var("rs2_val", instr_vars, arch_state)
@@ -492,6 +502,8 @@ def trap_registers_update(self, instr_vars, trap_dict):
         instr_vars['mode_change']   = trap_dict['mode_change']
         instr_vars['call_type']     = trap_dict['call_type']
 
+        mcause_interrupt = {32: 0x80000000, 64: 0x8000000000000000}
+
         if trap_dict["mode_change"] is not None:
             #update the registers depending upon the mode change
             if trap_dict["mode_change"].split()[2] == "M":
@@ -509,6 +521,17 @@ def trap_registers_update(self, instr_vars, trap_dict):
                 if "mcause" not in instr_vars:
                     instr_vars['mcause']      = None
                     instr_vars['mtval']       = None
+
+        #Handle interrupt Case
+        # TODO: update the interrupt case for delegation !
+        elif trap_dict["mode_change"] is None and trap_dict['call_type'] == "interrupt":
+                #upper most bit should be 1 in case of interrupt
+                instr_vars['mcause'] = mcause_interrupt[instr_vars['xlen']] | int(trap_dict['exc_num'], 16)
+                instr_vars['mtval']       = trap_dict['tval']
+                #only update on the initialization
+                if "scause" not in instr_vars:
+                    instr_vars['scause']      = None
+                    instr_vars['stval']       = None
 
         else:
                 #initialize them to None for the first time in the instr_vars

riscv-isac/riscv_isac/coverage.py

@@ -973,8 +973,8 @@ def old_fn_csr_comb_covpt(csr_reg):
             # if instr_vars["mode_change"] is not None:  #change the state only on the instruction
             csr_regfile["mcause"] = instr_vars["mcause"]
             csr_regfile["scause"] = instr_vars["scause"]
-            csr_regfile["mtval"] = instr_vars["mtval"]
-            csr_regfile["stval"] = instr_vars["stval"]
+            csr_regfile["mtval"]  = instr_vars["mtval"]
+            csr_regfile["stval"]  = instr_vars["stval"]
 
             if 'rs1' in instr_vars:
                 rs1 = instr_vars['rs1']

riscv-isac/riscv_isac/plugins/c_sail.py

@@ -20,7 +20,10 @@ def setup(self, trace, arch):
     instr_pattern_c_sail_csr_reg_val = re.compile('(?P<CSR>CSR|clint::tick)\s(?P<reg>[a-z0-9]+)\s<-\s(?P<val>[0-9xABCDEF]+)(?:\s\(input:\s(?P<input_val>[0-9xABCDEF]+)\))?')
     instr_pattern_c_sail_mem_val = re.compile('mem\[(?P<addr>[0-9xABCDEF]+)\]\s<-\s(?P<val>[0-9xABCDEF]+)')
     instr_pattern_c_sail_trap = re.compile(r'trapping\sfrom\s(?P<mode_change>\w+\sto\s\w+)\sto\shandle\s(?P<call_type>\w+.*)\shandling\sexc#(?P<exc_num>0x[0-9a-fA-F]+)\sat\spriv\s\w\swith\stval\s(?P<tval>0x[0-9a-fA-F]+)')
+    instr_pattern_c_sail_interrupt = re.compile(r'Handling\s(?P<call_type>\w+):\s(?P<intr_num>0x[0-9a-fA-F]+)\shandling\sint#0x[0-9a-fA-F]+\sat\spriv\s\w\swith\stval\s(?P<tval>0x[0-9a-fA-F]+)')
     instr_pattern_c_sail_ret  = re.compile(r'ret-ing\sfrom\s(?P<mode_change>\w+\sto\s\w+)')
+    instr_pattern_c_sail_mip = re.compile(r'\(mip\.(?P<bit>\w+)\s<-\s(?P<val>[0-9a-fA-F]+b[0-9a-fA-F]+)\)')
+# (?P<bit_type>)\s<-\s(?P<Bit_value>))
     def extractInstruction(self, line):
         instr_pattern = self.instr_pattern_c_sail
         re_search = instr_pattern.search(line)
@@ -123,8 +126,23 @@ def extractMemVal(self, line):
         else:
             return mem_val
 
+    def extractMIPVal(self, line):
+        '''
+        Function to extract the hart updated value of MIP CSR.        
+        return: int -> value updated in the MIP
+        '''
+        instr_pattern = self.instr_pattern_c_sail_mip.search(line)
+        mip = {'mei': 0x800, 'sei': 0x200, 'mti': 0x80, 'sti': 0x20,'msi': 0x8,'ssi': 0x2}
+
+        if instr_pattern:
+            if instr_pattern.group("bit").lower() in mip.keys():
+                return mip[instr_pattern.group("bit").lower()] * int(instr_pattern.group("val"), 2)
+            else:
+                return None
+
     def extracttrapvals(self, line):
         instr_trap_pattern = self.instr_pattern_c_sail_trap.search(line)
+        instr_interrupt_pattern  = self.instr_pattern_c_sail_interrupt.search(line)
         trap_dict = {"mode_change": None, "call_type": None, "exc_num": None, "tval": None}
 
         #ret will tell us to delete the previous state of the cause registers
@@ -136,12 +154,20 @@ def extracttrapvals(self, line):
             trap_dict["tval"]        = instr_trap_pattern.group("tval")
             self.old_trap_dict = trap_dict
 
+        #update the cause registers if there is interrupt
+        elif instr_interrupt_pattern:
+            trap_dict["mode_change"] = None
+            trap_dict["call_type"]   = instr_interrupt_pattern.group("call_type")
+            trap_dict["exc_num"]     = instr_interrupt_pattern.group("intr_num")
+            trap_dict["tval"]        = instr_interrupt_pattern.group("tval")
+            self.old_trap_dict = trap_dict
+
         elif instr_ret_pattern:
             #if ret_signal is 1 then clear the values of the mode_change, call_type, exc_num, tval
             trap_dict = {"mode_change": None, "call_type": None, "exc_num": None, "tval": None}
             self.old_trap_dict = trap_dict
 
-        #maintain the values if None unit the new trap appears
+        #maintain the values if None until the new trap appears
         if instr_trap_pattern is None or instr_ret_pattern is None:
             trap_dict = self.old_trap_dict
         return trap_dict
@@ -159,5 +185,6 @@ def __iter__(self):
             vm_addr_dict = self.extractVirtualMemory(line)
             mem_val = self.extractMemVal(line)
             trap_dict = self.extracttrapvals(line)
-            instrObj = instructionObject(instr, 'None', addr, reg_commit = reg_commit, csr_commit = csr_commit, mnemonic = mnemonic, mode = mode, vm_addr_dict = vm_addr_dict, mem_val = mem_val, trap_dict = trap_dict)
+            mip_updated_val = self.extractMIPVal(line)
+            instrObj = instructionObject(instr, 'None', addr, reg_commit = reg_commit, csr_commit = csr_commit, mnemonic = mnemonic, mode = mode, vm_addr_dict = vm_addr_dict, mem_val = mem_val, trap_dict = trap_dict, mip_updated_val = mip_updated_val)
             yield instrObj