QSPI flash support for Xilinx's Zynq devices
There are many problems around the flash programming of the Zynq FPGAs. The task becomes harder if there is no DDR memory, or the bootmode switch is unavailable, etc... This repo contains a simple flash util, to read, write, erase the QSPI flash attached to Zynq FPGAs.
An executable (flash_writer.elf) runs on the Zynq's ARM, which handles the QSPI interface itself, and gives an interface for the XSCT/XSDB TCL console. In the TCL console the flash_writer.tcl gives TCL procedures. These procedures communicate with the flash_writer.elf and command it to read, write, erase the QSPI flash.
You can use prebuilt flash_writer.elf executable or you can build it from scratch from the given sources.
You can try the prebuilt executables on ZEDBoard (or any board with 7Z020 device.)
- Open an XSCT console.
- Go to this repo's folder.
cd zynq_flash
- Source tcl sources:
source zed_bin/ps7_init.tcl
andsource flash_writer.tcl
- Connect and choose your ARM target:
connect
andtargets <num>
- Run all flashing operation (init, erase, write, verify) with one command:
flash_image zed_bin/boot.bin
(you can turn on/off erase, blank-check and verify) - Turn off/on the board and check the LEDs. If you have any problem feel free to contact me.
zed_bin_full_console.txt is a full log of a flash programming.
The flash writer executable has to be rebuilt for different architectures. Here is a small description of how to do that:
- Open Xilinx's XSDK.
- Create a new Application project. Use your own hardware-platform / board-support-package. Choose the empty application. The zed_bin/system.hdf hardware definition for ZedBoard, so you can use that hdf for ZedBoard flashing.
- Copy the three sources:
main.c
,flahs.c
flash.h
into your application project's sources. - Refresh or rebuild your project and check the output in the Debug directory.
This flash writer does not uses DDR-RAM or the Boot-mode switch. So the only requirement is the QSPI flash, which can be enabled for the Zynq in the Vivado's IP Integrator (aka. blockdesign) -> Zynq Processing system -> MIO Configuration -> Memory interfaces.