[CIRCT] Add minwidth to ensure endianness and vector width
#234
This workflow is awaiting approval from a maintainer in #32
Triggered via pull request
September 12, 2025 11:51
Scheremo
Status
Action required
Total duration
–
Artifacts
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This workflow is awaiting approval from a maintainer in #32
lint.yml
on: pull_request
Lint Verilog sources
lint-license