Debugging tips

This page contains some tips on how to interpret the VCD file generated by simulating the processor. To easily visualize what happens in each stage, it is best to always show a few common signals of all stages. Use the following as a starting point:

• in_PC: the program counter of the current instruction in the stage;
• in_IR: the instruction register. A helper script is provided (res/disas.py) to automatically disassemble this signal. It can be used by right-clicking on the signal in GTKWave and going to "Data Format" -> "Translate Filter Process" -> "Enable and Select". Make sure the RISC-V toolchain is in your PATH when using this script;
• arbitration_isValid: indicates when the current instruction is valid.

For convenience, we also provide a very basic GTKWave save file in sim.gtkw, which uses the helper script.

Multiple signals can be grouped by selecting them and pressing "G". It is useful to group all signals belonging to the same stage.