GitHub - pivaszbs/CA-Project: Simple design of cache and RAM

Name		Name	Last commit message	Last commit date
Latest commit History 55 Commits
.qsys_edit		.qsys_edit
MIPS		MIPS
Test_2		Test_2
db		db
incremental_db		incremental_db
output_files		output_files
simulation/modelsim		simulation/modelsim
cache.v		cache.v
cache.v.bak		cache.v.bak
cache_2way.v		cache_2way.v
cache_4way.v		cache_4way.v
cache_example.qpf		cache_example.qpf
cache_example.qsf		cache_example.qsf
cache_example.qws		cache_example.qws
cache_example.v		cache_example.v
cache_example.v.bak		cache_example.v.bak
cache_example_nativelink_simulation.rpt		cache_example_nativelink_simulation.rpt
ram.v		ram.v
ram.v.bak		ram.v.bak
ram_test_bench.v		ram_test_bench.v
ram_test_bench.v.bak		ram_test_bench.v.bak
rate_tb.v		rate_tb.v
rate_tb.v.bak		rate_tb.v.bak
simple_ram_tb.v		simple_ram_tb.v
simple_ram_tb.v.bak		simple_ram_tb.v.bak