Move everything latency counting related to latency/

Author: VonTum

src/flattening/mod.rs

@@ -3,7 +3,6 @@ mod initialization;
 mod lints;
 mod name_context;
 mod parser;
-mod port_latency_inference;
 mod typechecking;
 mod walk;
 
@@ -15,10 +14,10 @@ use crate::typing::type_inference::{DomainVariableIDMarker, TypeVariableIDMarker
 use std::cell::OnceCell;
 use std::ops::Deref;
 
+use crate::latency::port_latency_inference::PortLatencyInferenceInfo;
 pub use flatten::flatten_all_globals;
 pub use initialization::gather_initial_file_data;
 pub use lints::perform_lints;
-use port_latency_inference::PortLatencyInferenceInfo;
 pub use typechecking::typecheck_all_modules;
 
 use crate::linker::{Documentation, LinkInfo};
@@ -327,6 +326,8 @@ pub enum WireReferenceRoot {
     /// int local_var
     /// local_var = 3
     /// ```
+    ///
+    /// [FlatID] points to [Instruction::Declaration]
     LocalDecl(FlatID, Span),
     /// ```sus
     /// bool b = true // root is global constant `true`

src/instantiation/mod.rs

@@ -1,8 +1,5 @@
 mod concrete_typecheck;
 mod execute;
-mod latency_algorithm;
-mod latency_count;
-mod list_of_lists;
 mod unique_names;
 
 use unique_names::UniqueNames;
@@ -24,8 +21,6 @@ use crate::{
 
 use crate::typing::concrete_type::ConcreteType;
 
-use self::latency_algorithm::SpecifiedLatency;
-
 // Temporary value before proper latency is given
 pub const CALCULATE_LATENCY_LATER: i64 = i64::MIN;
 
@@ -38,7 +33,7 @@ pub enum RealWirePathElem {
 }
 
 impl RealWirePathElem {
-    fn for_each_wire_in_path(path: &[RealWirePathElem], mut f: impl FnMut(WireID)) {
+    pub fn for_each_wire_in_path(path: &[RealWirePathElem], mut f: impl FnMut(WireID)) {
         for v in path {
             match v {
                 RealWirePathElem::ArrayAccess { span: _, idx_wire } => {
@@ -318,24 +313,24 @@ pub struct ConditionStackElem {
 }
 
 /// As with other contexts, this is the shared state we're lugging around while executing & typechecking a module.
-struct InstantiationContext<'fl, 'l> {
-    name: String,
-    generation_state: GenerationState<'fl>,
-    wires: FlatAlloc<RealWire, WireIDMarker>,
-    submodules: FlatAlloc<SubModule, SubModuleIDMarker>,
+pub struct InstantiationContext<'fl, 'l> {
+    pub name: String,
+    pub wires: FlatAlloc<RealWire, WireIDMarker>,
+    pub submodules: FlatAlloc<SubModule, SubModuleIDMarker>,
 
-    type_substitutor: TypeSubstitutor<ConcreteType, ConcreteTypeVariableIDMarker>,
+    pub type_substitutor: TypeSubstitutor<ConcreteType, ConcreteTypeVariableIDMarker>,
 
-    // Used for Execution
+    /// Used for Execution
+    generation_state: GenerationState<'fl>,
     unique_name_producer: UniqueNames,
     condition_stack: Vec<ConditionStackElem>,
 
-    interface_ports: FlatAlloc<Option<InstantiatedPort>, PortIDMarker>,
-    errors: ErrorCollector<'l>,
+    pub interface_ports: FlatAlloc<Option<InstantiatedPort>, PortIDMarker>,
+    pub errors: ErrorCollector<'l>,
 
-    template_args: &'fl TVec<ConcreteType>,
-    md: &'fl Module,
-    linker: &'l Linker,
+    pub template_args: &'fl TVec<ConcreteType>,
+    pub md: &'fl Module,
+    pub linker: &'l Linker,
 }
 
 /// Mangle the module name for use in code generation

src/instantiation/latency_algorithm.rs renamed to src/latency/latency_algorithm.rs

@@ -1,17 +1,20 @@
+mod latency_algorithm;
+mod list_of_lists;
+pub mod port_latency_inference;
+
 use std::{cmp::max, iter::zip};
 
 use crate::prelude::*;
 
-use crate::{
-    flattening::{Instruction, WriteModifiers},
-    instantiation::latency_algorithm::{
-        convert_fanin_to_fanout, solve_latencies, FanInOut, LatencyCountingError,
-    },
+use crate::flattening::{Instruction, WriteModifiers};
+
+use latency_algorithm::{
+    convert_fanin_to_fanout, solve_latencies, FanInOut, LatencyCountingError, SpecifiedLatency,
 };
 
 use self::list_of_lists::ListOfLists;
 
-use super::*;
+use crate::instantiation::*;
 
 struct PathMuxSource<'s> {
     to_wire: &'s RealWire,

src/instantiation/list_of_lists.rs renamed to src/latency/list_of_lists.rs

@@ -6,7 +6,9 @@ use crate::{
     value::Value,
 };
 
-use super::{BinaryOperator, Instruction, Port, UnaryOperator, WireReference, WireReferenceRoot};
+use crate::flattening::{
+    BinaryOperator, Instruction, Port, UnaryOperator, WireReference, WireReferenceRoot,
+};
 
 /*/// ports whose latency annotations require them to be at fixed predefined offsets
 ///

src/instantiation/latency_count.rs renamed to src/latency/mod.rs

@@ -9,6 +9,7 @@ mod errors;
 mod file_position;
 mod flattening;
 mod instantiation;
+mod latency;
 mod prelude;
 mod to_string;
 mod typing;

src/flattening/port_latency_inference.rs renamed to src/latency/port_latency_inference.rs

@@ -1118,3 +1118,9 @@ module IfTesting #(int WIDTH) {
         } else when WIDTH > BASE_CASE_SIZE {
         }
 }
+
+module test {
+	gen int[2] p
+
+	int zsda = p[0]
+}