-
Notifications
You must be signed in to change notification settings - Fork 4
/
bad_syntax.sus
183 lines (142 loc) · 3.08 KB
/
bad_syntax.sus
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
// A file for bad or old syntaxes.
// This is there to check for ICEs
module multiply {
interface multiply : int a, int b -> int r
r = a * b
}
// test
module contains_submodule {
interface contains_submodule : int a, int b, int c -> int r
int tmp = multiply(a, b)
reg r = tmp + c
}
template<int Size>
module ExactlyOne {
interface ExactlyOne : bool[Size] inputs -> bool exactlyOne
if Size == 0 {
exactlyOne = false
} else if Size == 1 {
exactlyOne = inputs[0]
} else {
bool[Size] atLeastOnes
bool[Size] atLeastTwos
atLeastOnes[0] = inputs[0]
atLeastTwos[0] = false
for i in 1:Size {
atLeastOnes[i] = atLeastOnes[i-1] | inputs[i]
atLeastTwos[i] = atLeastTwos[i-1] | atLeastOnes[i-1] & inputs[i]
}
exactlyOne = atLeastOnes & !atLeastTwos
}
}
module parallel_mul_add_reg {
interface parallel_mul_add_reg : int a, int b -> int p, int q
reg int a2 = a * a
reg int a3 = a * a2 + 3
reg p = a * a3
reg int b2 = b + b
reg int b3 = b + b2
reg q = b + b3
// UTF-8 Characters support
Lööwe 老虎
}
/*
a
b
c
tmp
result
*/
timeline (v v _ -> _) .. (_ _ v -> v)
module mul_add {
interface mul_add : int a, int b, int c -> int result
reg int tmp = a * b
result = tmp + c
}
/* a module to test the syntax */
module MultiplyAdd {
interface MultiplyAdd : i32 a, i32 b, i32 c -> i32 result
// temporary variable
i32 tmp = a * b
result = tmp + cooo * 30 + 5
array_subscript = tmp
{
//[
beep boop
}
@
int[5] myVar
myVar[0] = 0
myVar[1] = 1
myVar[2] = 2
myVar[3] = 3
myVar[4] = 4
@
}
module beep {
interface beep : i32 a
state i32 beep
beep = 5
#
beep = a
}
timeline (a -> r) .. (/ -> r)
module dwiogo {
interface dwiogo : bool[512] data -> bool[256] out
state bool[256] save = data[256:511]
out = data[0:255]
#
out = save
}
timeline (v, true -> v) .. (/, false -> v) .. (/, false -> v) .. (/, false -> v)
module packer {
interface packer : bool[256] data /* v _ _ _ */, bool valid -> bool[64] o /* v v v v */
state bool[192] save = data[64:256]
state int part
initial part = 3
if valid {
part = 0
o = data[0:64]
} else {
o = save[part*64 - 64:part*64]
if part < 3 {
part = part + 1
}
}
}
module multiply_add_old {
interface multiply_add_old : i32 a, i32 b, i32 c -> i32 result, double double_result
i32 tmp = a * b
reg result = tmp + c
reg double_result = cvt_to_double(result)
}
module exists {
interface exists : hello a -> int result
}
module hello {
interface hello : int a -> int b }
module test_exists {
interface test_exists : -> int result
int x = exists(5)
int b = doesnt_exist(3)
}
module exists {
interface exists : duplicate a
// Should be a duplicate of previous exists
}
module use_other_file {
interface use_other_file : int a -> int r
r = hello_from_the_other_side(a)
}
interface maemory_read : int addr -> bool[16] data
//HandShake hs = hs_0
module test_hs {
state int st = 5
gen if HA_HANDSHAKE {}
interface hs {
interface boop {
}
}
interface process : int[10] data -> int[9] data {
}
}