Bias pin handling

[dsengupta0628]

This change adds explicit bias-pin classification to OpenSTA by introducing PortDirection::bias() and mapping Liberty nwell/pwell/deepnwell/deeppwell pg pins to it. By including bias in isPowerGround(), bias pins are now treated like power/ground in existing STA and Verilog-writer filtering paths, fixing cases where write_verilog incorrectly emitted bias pins as signal pins.

A new regression was added in test/verilog_bias_pins.* using the existing examples/sky130hd_tt.lib.gz library to cover both default write_verilog behavior and write_verilog -include_pwr_gnd, with goldens updated to match the current binary output.

(Reference: https://dl.acm.org/doi/pdf/10.1145/2333660.2333679 typical bias pin handling is needed for body bias calculations and not really in timing graph just like the power/ground pins)

[jjcherry56]

Let's start with the name; I think these would be more appropriately called "well" supplies than "bias".

[dsengupta0628]

Let's start with the name; I think these would be more appropriately called "well" supplies than "bias".

Done.