[LibertyClk] Support for Liberty file defined generated clock

CMakeLists.txt

@@ -114,6 +114,7 @@ set(STA_SOURCE
   liberty/TimingRole.cc
   liberty/Units.cc
   liberty/Wireload.cc
+  liberty/GeneratedClock.cc
 
   network/ConcreteLibrary.cc
   network/ConcreteNetwork.cc

include/sta/Clock.hh

@@ -294,5 +294,7 @@ sortByName(ClockSet *set);
 int
 compare(const ClockSet *set1,
         const ClockSet *set2);
+bool
+isPowerofTwo(int i);
 
 } // namespace

include/sta/GeneratedClock.hh

@@ -0,0 +1,46 @@
+#pragma once
+
+#include "LibertyClass.hh"
+#include "SdcClass.hh"
+
+namespace sta {
+
+class GeneratedClock
+{
+public:
+  ~GeneratedClock();
+  const char *name() const { return name_; }
+  const char *clockPin() const { return clock_pin_; }
+  const char *masterPin() const { return master_pin_; }
+  int dividedBy() const { return divided_by_; }
+  int multipliedBy() const { return multiplied_by_; }
+  float dutyCycle() const { return duty_cycle_; }
+  bool invert() const { return invert_; }
+  IntSeq *edges() const { return edges_; }
+  FloatSeq *edgeShifts() const { return edge_shifts_; }
+
+protected:
+  GeneratedClock(const char *name,
+                 const char *clock_pin,
+                 const char *master_pin,
+                 int divided_by,
+                 int multiplied_by,
+                 float duty_cycle,
+                 bool invert,
+                 IntSeq *edges,
+                 FloatSeq *edge_shifts);
+
+  const char *name_;
+  const char *clock_pin_;
+  const char *master_pin_;
+  int divided_by_;
+  int multiplied_by_;
+  float duty_cycle_;
+  bool invert_;
+  IntSeq *edges_;
+  FloatSeq *edge_shifts_;
+
+  friend class LibertyCell;
+};
+
+} // namespace

include/sta/Liberty.hh

@@ -36,6 +36,7 @@
 #include "Transition.hh"
 #include "Delay.hh"
 #include "LibertyClass.hh"
+#include "SdcClass.hh"
 
 namespace sta {
 
@@ -483,6 +484,8 @@ public:
   const SequentialSeq &sequentials() const { return sequentials_; }
   // Find the sequential with the output connected to an (internal) port.
   Sequential *outputPortSequential(LibertyPort *port);
+  // Generated clocks.
+  const GeneratedClockSeq &generatedClocks() const { return generated_clocks_; }
   const Statetable *statetable() const { return statetable_; }
 
   // Find bus declaration local to this cell.
@@ -509,6 +512,15 @@ public:
   OcvDerate *findOcvDerate(const char *derate_name);
 
   // Build helpers.
+  void makeGeneratedClock(const char *name,
+			  const char *clock_pin,
+			  const char *master_pin,
+			  int divided_by,
+			  int multiplied_by,
+			  float duty_cycle,
+			  bool invert,
+			  IntSeq *edges,
+			  FloatSeq *edge_shifts);
   void makeSequential(int size,
 		      bool is_register,
 		      FuncExpr *clk,
@@ -621,6 +633,7 @@ protected:
   PortInternalPowerSeq port_internal_powers_;
   InternalPowerAttrsSeq internal_power_attrs_;
   LeakagePowerSeq leakage_powers_;
+  GeneratedClockSeq generated_clocks_;
   SequentialSeq sequentials_;
   PortToSequentialMap port_to_seq_map_;
   Statetable *statetable_;

include/sta/LibertyClass.hh

@@ -56,6 +56,7 @@ class TimingArc;
 class TimingArcAttrs;
 class InternalPower;
 class LeakagePower;
+class GeneratedClock;
 class Sequential;
 class FuncExpr;
 class TimingModel;
@@ -70,6 +71,7 @@ class StatetableRow;
 typedef Vector<LibertyLibrary*> LibertyLibrarySeq;
 typedef Vector<LibertyCell*> LibertyCellSeq;
 typedef Vector<Sequential*> SequentialSeq;
+typedef Vector<GeneratedClock*> GeneratedClockSeq;
 typedef Map<LibertyCell*, LibertyCellSeq*> LibertyCellEquivMap;
 typedef Vector<LibertyPort*> LibertyPortSeq;
 typedef Set<LibertyPort*> LibertyPortSet;

include/sta/Network.hh

@@ -443,6 +443,12 @@ public:
   virtual char pathEscape() const { return escape_; }
   virtual void setPathEscape(char escape);
 
+  // Generated clocks related functions
+  void addGeneratedClockPinToCell(const char *pinName, LibertyCell *cell);
+  const Map<const char*, LibertyCell*> &generatedClockPinsToCellMap() const {
+    return generated_clock_pins_to_cells_;
+  }
+
 protected:
   Pin *findPinLinear(const Instance *instance,
 		     const char *port_name) const;
@@ -497,6 +503,9 @@ protected:
   char divider_;
   char escape_;
   NetDrvrPinsMap net_drvr_pin_map_;
+
+  // Map of generated clock pins to their corresponding liberty cell
+  Map<const char*, LibertyCell*> generated_clock_pins_to_cells_;
 };
 
 // Network API to support network edits.

include/sta/Sdc.hh

@@ -376,6 +376,7 @@ public:
 		      float fanout);
   void setMaxArea(float area);
   float maxArea() const;
+  void createLibertyGeneratedClocks(Clock *clk);
   Clock *makeClock(const char *name,
                    PinSet *pins,
                    bool add_to_pins,

include/sta/Sta.hh

@@ -298,10 +298,14 @@ public:
   void removeClock(Clock *clk);
   // Update period/waveform for generated clocks from source pin clock.
   void updateGeneratedClks();
+  // Mark that generated clocks need to be updated.
+  void setUpdateGenclks();
   // True if pin is defined as a clock source (pin may be hierarchical).
   bool isClockSrc(const Pin *pin) const;
   // Propagated (non-ideal) clocks.
   void setPropagatedClock(Clock *clk);
+  //Mark that generated clocks to be updated
+  void setUpdatedGenclks();
   void removePropagatedClock(Clock *clk);
   void setPropagatedClock(Pin *pin);
   void removePropagatedClock(Pin *pin);

include/sta/StringUtil.hh

@@ -199,6 +199,13 @@ isTmpString(const char *str);
 void
 trimRight(std::string &str);
 
+// Trim left spaces.
+void
+trimLeft(std::string &str);
+
+void
+trim(std::string &str);
+
 typedef Vector<std::string> StringVector;
 
 void

liberty/GeneratedClock.cc

@@ -0,0 +1,43 @@
+#include "GeneratedClock.hh"
+
+#include "Liberty.hh"
+#include "StringUtil.hh"
+
+namespace sta {
+
+GeneratedClock::GeneratedClock(const char *name,
+                                const char *clock_pin,
+                                const char *master_pin,
+                                int divided_by,
+                                int multiplied_by,
+                                float duty_cycle,
+                                bool invert,
+                                IntSeq *edges,
+                                FloatSeq *edge_shifts) :
+  name_(name ? stringCopy(name) : nullptr),
+  clock_pin_(clock_pin ? stringCopy(clock_pin) : nullptr),
+  master_pin_(master_pin ? stringCopy(master_pin) : nullptr),
+  divided_by_(divided_by),
+  multiplied_by_(multiplied_by),
+  duty_cycle_(duty_cycle),
+  invert_(invert),
+  edges_(edges),
+  edge_shifts_(edge_shifts)
+{
+}
+
+GeneratedClock::~GeneratedClock()
+{
+  if (name_)
+    stringDelete(name_);
+  if (clock_pin_)
+    stringDelete(clock_pin_);
+  if (master_pin_)
+    stringDelete(master_pin_);
+  if (edges_)
+    delete edges_;
+  if (edge_shifts_)
+    delete edge_shifts_;
+}
+
+} // namespace

liberty/Liberty.cc

@@ -41,6 +41,7 @@
 #include "InternalPower.hh"
 #include "LeakagePower.hh"
 #include "Sequential.hh"
+#include "GeneratedClock.hh"
 #include "Wireload.hh"
 #include "EquivCells.hh"
 #include "Network.hh"
@@ -969,6 +970,7 @@ LibertyCell::~LibertyCell()
   leakage_powers_.deleteContents();
 
   sequentials_.deleteContents();
+  generated_clocks_.deleteContents();
   delete statetable_;
   bus_dcls_.deleteContents();
   scaled_cells_.deleteContents();
@@ -1474,6 +1476,43 @@ LibertyCell::hasTimingArcs(LibertyPort *port) const
     || timing_arc_set_to_map_.findKey(port);
 }
 
+void
+LibertyCell::makeGeneratedClock(const char *name,
+				 const char *clock_pin,
+				 const char *master_pin,
+				 int divided_by,
+				 int multiplied_by,
+				 float duty_cycle,
+				 bool invert,
+				 IntSeq *edges,
+				 FloatSeq *edge_shifts)
+{
+  // Copy edges and edge_shifts if they exist
+  IntSeq *edges_copy = nullptr;
+  if (edges) {
+    edges_copy = new IntSeq(*edges);
+  }
+
+  FloatSeq *edge_shifts_copy = nullptr;
+  if (edge_shifts) {
+    edge_shifts_copy = new FloatSeq(*edge_shifts);
+  }
+
+  // Create the GeneratedClock object
+  GeneratedClock *generated_clock = new GeneratedClock(
+    name,
+    clock_pin,
+    master_pin,
+    divided_by,
+    multiplied_by,
+    duty_cycle,
+    invert,
+    edges_copy,
+    edge_shifts_copy
+  );
+  generated_clocks_.push_back(generated_clock);
+}
+
 void
 LibertyCell::makeSequential(int size,
 			    bool is_register,