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    70 repositories

    • seal5

      Public
      Seal5 - Semi-automated LLVM Support for RISC-V Extensions including Autovectorization
      compilerllvmriscvrisc-viselretargetingcoredslcoredsl2
      Python
      •
      Apache License 2.0
      •7•17•58•5•Updated Apr 14, 2025Apr 14, 2025

    • M2-ISA-R

      Public
      CoreDSL2 Parser with backend to generate simulation code for the ETISS instruction set simulator
      Python
      •
      Apache License 2.0
      •7•7•12•5•Updated Apr 9, 2025Apr 9, 2025

    • PerformanceSimulation_workspace

      Public
      Example workspace for software performance simulation with ETISS-based performance simulator
      Python
      •
      Apache License 2.0
      •3•2•0•0•Updated Mar 26, 2025Mar 26, 2025

    • etiss-perf-sim

      Public
      ETISS-based performance simulator
      C++
      •
      Apache License 2.0
      •3•1•0•0•Updated Mar 26, 2025Mar 26, 2025

    • SoftwareEvalLib

      Public
      C++
      •
      Apache License 2.0
      •2•1•0•0•Updated Mar 26, 2025Mar 26, 2025

    • SoftwareEval-Backends

      Public
      C++
      •
      Apache License 2.0
      •1•1•0•0•Updated Mar 26, 2025Mar 26, 2025

    • mlonmcu-sw

      Public
      Target software library (MLIF, Machine Learning Interface) used by the MLonMCU python package
      C
      •3•1•3•5•Updated Mar 24, 2025Mar 24, 2025

    • isaac-toolkit

      Public
      Automated Customization Toolkit for Instruction Set Architectures (ISAs)
      Python
      •
      Apache License 2.0
      •0•0•0•0•Updated Mar 24, 2025Mar 24, 2025

    • mlonmcu

      Public
      Tool for the deployment and analysis of TinyML applications on TFLM and MicroTVM backends
      Python
      •
      Apache License 2.0
      •12•34•52•13•Updated Mar 24, 2025Mar 24, 2025

    • etiss-arch-plugins

      Public
      Out-ouf-tree ArchImpl plugins for ETISS
      Makefile
      •0•0•0•0•Updated Mar 21, 2025Mar 21, 2025

    • CorePerfDSL-Examples

      Public
      Examples of CorePerfDSL descriptions
      Apache License 2.0
      •0•0•0•0•Updated Mar 19, 2025Mar 19, 2025

    • M2-ISA-R-Perf

      Public
      Python
      •
      Apache License 2.0
      •0•1•0•0•Updated Mar 19, 2025Mar 19, 2025

    • micro-kws

      Public
      Complete flow for keyword spotting on microcontrollers. From data collection to data preparation to training and deployment.
      Jupyter Notebook
      •0•4•0•0•Updated Mar 10, 2025Mar 10, 2025

    • muriscv-nn

      Public
      muRISCV-NN is a collection of efficient deep learning kernels for embedded platforms and microcontrollers.
      C++
      •
      Apache License 2.0
      •10•76•34•3•Updated Mar 6, 2025Mar 6, 2025

    • etiss_riscv_tests

      Public
      C++
      •
      Apache License 2.0
      •0•0•0•0•Updated Mar 6, 2025Mar 6, 2025

    • CoreV_ISA_CoreDSL

      Public
      CoreDSL descriptions of the Core-V ISA Extension (https://cv32e40p.readthedocs.io/en/latest/instruction_set_extensions.html)
      Roff
      •2•0•0•0•Updated Mar 5, 2025Mar 5, 2025

    • softvector

      Public
      Vector arithmetic library targeting simulation of Vector Processing Units (VPUs) for various targets, e.g., ETISS.
      C++
      •
      Apache License 2.0
      •5•3•0•0•Updated Mar 4, 2025Mar 4, 2025

    • etiss_riscv_examples

      Public
      C
      •8•2•0•0•Updated Feb 27, 2025Feb 27, 2025

    • etiss

      Public
      Extendable Translating Instruction Set Simulator
      risc-vinstruction-set-simulator
      C++
      •
      Other
      •40•29•16•8•Updated Feb 17, 2025Feb 17, 2025

    • etiss_riscv_examples_s4e

      Public
      C++
      •8•0•0•0•Updated Jan 24, 2025Jan 24, 2025

    • etiss-sc

      Public
      SystemC/TLM2.0 productivity library wrapping the Extendable Instruction Set Simulator ETISS as a tlm cpu core.
      C++
      •
      Apache License 2.0
      •2•4•0•1•Updated Jan 13, 2025Jan 13, 2025

    • etiss_riscv_test_env

      Public
      CI/CD Scripts for Evaluating the End-to-End "CoreDSL -> M2-ISA-R -> ETISS -> Test" Flow
      Python
      •1•0•0•0•Updated Oct 31, 2024Oct 31, 2024

    • riscv-coredsl-extensions

      Public
      Assembly
      •5•0•0•0•Updated Oct 31, 2024Oct 31, 2024

    • riscv-tests

      Public
      C
      •
      Other
      •497•0•0•0•Updated Sep 10, 2024Sep 10, 2024

    • mlonmcu-models

      Public
      TinyML model zoo primarily used by the MLonMCU python package
      Jupyter Notebook
      •
      MIT License
      •1•1•1•0•Updated Sep 9, 2024Sep 9, 2024

    • vrtlmod

      Public
      vRTLmod modifies Verilator generated RTL simulation code for faul-injection purposes. It transforms source code with the help of LLVM/Clang-Tools and generates a fault injection API.
      llvmclangfault-injectionverilatorregister-transfer-level
      C++
      •
      Apache License 2.0
      •5•13•2•1•Updated Sep 4, 2024Sep 4, 2024

    • etiss-accelerator-plugins

      Public
      C++
      •
      Apache License 2.0
      •0•0•0•0•Updated Sep 4, 2024Sep 4, 2024

    • Trace-Generator

      Public
      Python tool to generate monitors (and printers) for ETISS based on json description
      Python
      •
      Apache License 2.0
      •0•2•0•0•Updated Aug 19, 2024Aug 19, 2024

    • seminar_generator

      Public
      Excel generator for the student seminars (GradingSheets, Agenda, GradingReport)
      Python
      •0•0•0•0•Updated Jul 1, 2024Jul 1, 2024

    • etiss_arch_riscv

      Public
      RISC-V architecture models for ETISS
      9•0•0•0•Updated May 8, 2024May 8, 2024