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    67 repositories

    • cva6

      Public
      The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configurations are capable of bo…
      asiccpufpga
      asiccpufpgarisc-vsystemverilog-hdlrv64gcariane
      Assembly
      •
      Other
      •986•3k•221•16•Updated Jul 27, 2026Jul 27, 2026

    • core-v-mcu

      Public
      This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
      microcontrollerriscvsystemverilog
      microcontrollerriscvsystemverilogopenhwgroup
      SystemVerilog
      •
      Other
      •77•209•78•9•Updated Jul 27, 2026Jul 27, 2026

    • cv32e40s-dv

      Public
      CV32E40S Design-Verification environment
      Assembly
      •
      Apache License 2.0
      •3•1•1•0•Updated Jul 27, 2026Jul 27, 2026

    • uap

      Public
      Unified RISC-V Access Platform (UAP) project repository
      JavaScript
      •
      Eclipse Public License 2.0
      •52•27•7•0•Updated Jul 27, 2026Jul 27, 2026

    • cvfpu

      Public
      Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.
      SystemVerilog
      •
      Apache License 2.0
      •170•623•41•9•Updated Jul 24, 2026Jul 24, 2026

    • cv-hpdcache

      Public
      RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
      SystemVerilog
      •
      Other
      •53•110•2•3•Updated Jul 23, 2026Jul 23, 2026

    • cvw

      Public
      CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, support for A, B, C, D, F, …
      SystemVerilog
      •
      Other
      •549•588•22•7•Updated Jul 19, 2026Jul 19, 2026

    • cv32e20-dv

      Public
      Assembly
      •
      Apache License 2.0
      •12•4•4•7•Updated Jul 17, 2026Jul 17, 2026

    • cve2

      Public
      The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work f…
      SystemVerilog
      •
      Apache License 2.0
      •778•67•158•13•Updated Jul 17, 2026Jul 17, 2026

    • core-v-verif

      Public
      Functional verification project for the CORE-V family of RISC-V cores.
      verificationsystemveriloguvm
      verificationsystemveriloguvmrisc-v
      Assembly
      •
      Other
      •320•704•132•25•Updated Jul 17, 2026Jul 17, 2026

    • openhwfoundation.org

      Public
      OpenHW Group is a global, not-for-profit organization where hardware and software designers collaborate on open-source cores, IP, tools, and software. It provid…
      hugowebdev
      hugowebdev
      HTML
      •
      Eclipse Public License 2.0
      •10•19•9•8•Updated Jun 30, 2026Jun 30, 2026

    • cvfpu-uvm

      Public
      UVM Verification Environment for the CVFPU
      Perl
      •
      Other
      •10•23•3•3•Updated Jun 23, 2026Jun 23, 2026

    • core-et-erbium

      Public
      CORE-ET Silicon Platform erbium
      Verilog
      •
      Apache License 2.0
      •6•3•0•1•Updated Jun 23, 2026Jun 23, 2026

    • cva6-dcls

      Public
      Dual-Core-Lock-Step platform for the CVA6 RISC-V processor core
      Other
      •2•2•3•0•Updated Jun 3, 2026Jun 3, 2026

    • cv32e40x-dv

      Public
      CV32E40X Design-Verification environment
      Assembly
      •
      Other
      •10•18•4•1•Updated Jun 2, 2026Jun 2, 2026

    • cv32e40p-dv-review

      Public
      CV32E40P DV environment based on cv32e20-dv
      Assembly
      •
      Apache License 2.0
      •3•1•3•4•Updated Jun 2, 2026Jun 2, 2026

    • cv32e40p

      Public
      CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform
      riscvriscv32imfc
      riscvriscv32imfc
      SystemVerilog
      •
      Other
      •544•1.3k•59•18•Updated May 29, 2026May 29, 2026

    • core-et

      Public
      CORE-ET Silicon Platform
      SystemVerilog
      •
      Apache License 2.0
      •17•77•3•3•Updated May 7, 2026May 7, 2026

    • osdforum.org

      Public
      The Open Source Developer Forum is a workshop that brings open source software and hardware (chips, boards and systems) developers together to collaborate and l…
      hugowebdev
      hugowebdev
      HTML
      •
      Eclipse Public License 2.0
      •5•1•0•0•Updated Apr 7, 2026Apr 7, 2026

    • core-v-xif

      Public
      RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
      SystemVerilog
      •
      Other
      •31•91•20•3•Updated Apr 1, 2026Apr 1, 2026

    • core-v-cores

      Public
      CORE-V Family of RISC-V Cores
      26•364•1•1•Updated Mar 31, 2026Mar 31, 2026

    • .github

      Public
      1•0•0•0•Updated Mar 30, 2026Mar 30, 2026

    • cva6-sdk

      Public
      CVA6 SDK containing RISC-V tools and Buildroot
      Makefile
      •
      GNU General Public License v2.0
      •101•80•35•3•Updated Mar 27, 2026Mar 27, 2026

    • cva6-safe

      Public
      A dual-core lockstep (DCLS) subsystem for the CVA6. Also supports dual-core asymmetric multi-processing (AMP) when lockstep in not needed.
      SystemVerilog
      •
      Other
      •5•2•0•0•Updated Mar 26, 2026Mar 26, 2026

    • meta-cva6-yocto

      Public
      Yocto layer for CVA6
      BitBake
      •
      MIT License
      •7•6•0•2•Updated Jan 26, 2026Jan 26, 2026

    • programs

      Public
      Documentation for the OpenHW Group's set of CORE-V RISC-V cores
      HTML
      •
      Other
      •98•228•9•9•Updated Jan 11, 2026Jan 11, 2026

    • cv-hpdcache-verif

      Public
      Verification environment for the OpenHW Group's CORE-V High Performance Data Cache controller.
      SystemVerilog
      •
      Apache License 2.0
      •10•26•0•1•Updated Jan 6, 2026Jan 6, 2026

    • cvw-arch-verif

      Public
      The purpose of the repo is to support CORE-V Wally architectural verification
      SystemVerilog
      •
      Other
      •40•19•9•1•Updated Nov 11, 2025Nov 11, 2025

    • u-boot

      Public
      Unofficial development fork of U-Boot
      C
      •20•1•1•0•Updated Oct 15, 2025Oct 15, 2025

    • cva5

      Public
      The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
      SystemVerilog
      •
      Apache License 2.0
      •35•136•4•0•Updated Jul 11, 2025Jul 11, 2025
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