Search results

Determine if vmv1r.v and related instructions should trap when vill = 1

Status: Open.

#1810 In openhwgroup/cvw;

· davidharrishmc opened on Jul 24, 2026

Wally should produce an access fault rather than misaligned fault on misaligned LRSC

Status: Open.

#1809 In openhwgroup/cvw;

· davidharrishmc opened on Jul 23, 2026

cvw wfi lockstep mismatch

Status: Open.

#1808 In openhwgroup/cvw;

· davidharrishmc opened on Jul 23, 2026

cvw-rv64gc ExceptionsSvZalrsc/Zaamo ACT4 failures

Status: Open.

#1807 In openhwgroup/cvw;

· davidharrishmc opened on Jul 23, 2026

Benchmarking chapter table 21.1 -fno-tree-loop-distribute-patterns has no meaning

Status: Open.

#1805 In openhwgroup/cvw;

· JamesTimothyMeech opened on Jul 19, 2026

cvw should only count hpmevents when mhpmevent is nonzero

Status: Open.

#1802 In openhwgroup/cvw;

· davidharrishmc opened on Jul 15, 2026

InterruptsU/S mismatch in lockstep with ImperasDV

Status: Open.

#1787 In openhwgroup/cvw;

· davidharrishmc opened on Jun 14, 2026

LW reads wrong value when a Dcache miss overlaps with ITLB miss

Status: Open.

Bug

#1766 In openhwgroup/cvw;

· Zain2050 opened on May 17, 2026

Found some bugs while running regression for SV48

bugSomething isn't workingSomething isn't working

Status: Open.

#1538 In openhwgroup/cvw;

· Zain2050 opened on Oct 18, 2025

There is no exception when accessing unimplemented registers in RV32E mode

enhancementNew feature or requestNew feature or request

Status: Open.

#1513 In openhwgroup/cvw;

· Pablotpa opened on Aug 25, 2025

ParseHPMC.py giving incorrect results

Status: Open.

#1379 In openhwgroup/cvw;

· jordancarlin opened on Apr 23, 2025

OpenSBI Bug

enhancementNew feature or requestNew feature or request

Status: Open.

#1264 In openhwgroup/cvw;

· rosethompson opened on Feb 6, 2025