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    37 repositories

    • sv-tests

      Public
      Test suite designed to check compliance with the SystemVerilog standard.
      SystemVerilog
      •
      ISC License
      •82•0•0•0•Updated May 31, 2025May 31, 2025

    • silisizer

      Public
      Operator resize
      C++
      •
      GNU General Public License v3.0
      •2•2•0•0•Updated May 30, 2025May 30, 2025

    • OpenSTA

      Public
      OpenSTA Silimate fork
      C++
      •
      GNU General Public License v3.0
      •36•0•0•0•Updated May 30, 2025May 30, 2025

    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      •
      ISC License
      •953•0•0•0•Updated May 30, 2025May 30, 2025

    • sv-tests-results

      Public
      Output of the sv-tests runs.
      HTML
      •6•0•0•0•Updated May 30, 2025May 30, 2025

    • netlistsvg

      Public
      draws an SVG schematic from a JSON netlist
      JavaScript
      •
      MIT License
      •89•0•0•0•Updated May 30, 2025May 30, 2025

    • void

      Public
      TypeScript
      •
      Apache License 2.0
      •1.5k•0•0•0•Updated May 29, 2025May 29, 2025

    • yosys-slang

      Public
      SystemVerilog frontend for Yosys
      C++
      •
      ISC License
      •17•0•0•0•Updated May 28, 2025May 28, 2025

    • Digital-IDE

      Public
      All in one vscode plugin for HDL development
      VHDL
      •
      MIT License
      •62•0•0•0•Updated May 28, 2025May 28, 2025

    • vscode-terosHDL

      Public
      VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
      VHDL
      •
      GNU General Public License v3.0
      •53•0•0•0•Updated May 22, 2025May 22, 2025

    • liberty2json

      Public
      A simple converter from Liberty to JSON
      C
      •
      Other
      •3•0•0•1•Updated May 20, 2025May 20, 2025

    • vcd2fst

      Public
      Convert VCD waveform file to FST waveform file
      C
      •1•1•0•0•Updated May 16, 2025May 16, 2025

    • vscode-verilog-hdl-support

      Public
      HDL support for VS Code
      TypeScript
      •
      MIT License
      •81•0•0•0•Updated May 14, 2025May 14, 2025

    • sunburst-chart

      Public
      A sunburst interactive chart web component for visualizing hierarchical data
      JavaScript
      •
      MIT License
      •95•0•0•0•Updated May 1, 2025May 1, 2025

    • abc

      Public
      ABC: System for Sequential Logic Synthesis and Formal Verification
      C
      •
      Other
      •632•0•0•0•Updated Apr 27, 2025Apr 27, 2025

    • dspy

      Public
      DSPy: The framework for programming—not prompting—language models
      Python
      •
      MIT License
      •1.9k•0•0•0•Updated Apr 8, 2025Apr 8, 2025

    • mastra

      Public
      The TypeScript AI agent framework. ⚡ Assistants, RAG, observability. Supports any LLM: GPT-4, Claude, Gemini, Llama.
      TypeScript
      •
      Other
      •771•0•0•0•Updated Mar 10, 2025Mar 10, 2025

    • sdc2.1

      Public
      Synopsys SDC 2.1 Parser
      Tcl
      •0•1•0•0•Updated Dec 28, 2024Dec 28, 2024

    • verismith

      Public
      Verilog Fuzzer to test the major simulators and sythesisers by generating random, valid Verilog.
      Haskell
      •
      GNU General Public License v3.0
      •13•0•0•0•Updated Nov 14, 2024Nov 14, 2024

    • OpenRAM

      Public
      An open-source static random access memory (SRAM) compiler.
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •222•0•0•0•Updated Nov 14, 2024Nov 14, 2024

    • liberty-parser

      Public
      Synopsys's Liberty parser library
      C
      •
      Other
      •11•0•0•0•Updated Nov 13, 2024Nov 13, 2024

    • mg-verilog

      Public
      Python
      •
      MIT License
      •8•0•0•0•Updated Oct 14, 2024Oct 14, 2024

    • verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      C++
      •
      GNU Lesser General Public License v3.0
      •670•0•0•0•Updated Sep 3, 2024Sep 3, 2024

    • verilog-eval

      Public
      Verilog evaluation benchmark for large language model
      SystemVerilog
      •
      Other
      •48•0•0•0•Updated Aug 21, 2024Aug 21, 2024

    • iEDA

      Public archive
      Silimate iEDA fork
      C++
      •
      Other
      •44•0•0•0•Updated Aug 1, 2024Aug 1, 2024

    • chipgptv

      Public
      Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation (ICCAD 2024)
      Verilog
      •3•4•0•0•Updated Jul 11, 2024Jul 11, 2024

    • chipgptft

      Public
      Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
      Python
      •6•0•0•0•Updated Jul 11, 2024Jul 11, 2024

    • RTL-Coder

      Public
      A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.
      Python
      •22•0•0•0•Updated Jul 7, 2024Jul 7, 2024

    • tbengy

      Public
      Python Tool for UVM Testbench Generation
      Python
      •
      MIT License
      •18•0•0•0•Updated May 19, 2024May 19, 2024

    • VGen

      Public
      Jupyter Notebook
      •
      Apache License 2.0
      •9•0•0•0•Updated Apr 30, 2024Apr 30, 2024