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    • Nuitka

      Public
      Nuitka is a Python compiler written in Python. It's fully compatible with Python 2.6, 2.7, 3.4-3.13. You feed it your Python app, it does a lot of clever thing…
      Python
      765000Updated Feb 25, 2026Feb 25, 2026
    • yosys

      Public
      Yosys Open SYnthesis Suite
      C++
      1k002Updated Feb 25, 2026Feb 25, 2026
    • Liberty to JSON converter
      Verilog
      0300Updated Feb 24, 2026Feb 24, 2026
    • Output of the sv-tests runs.
      HTML
      6000Updated Feb 24, 2026Feb 24, 2026
    • vcd2fst

      Public
      Convert VCD waveform file to FST waveform file
      C
      1100Updated Feb 23, 2026Feb 23, 2026
    • rust_hdl

      Public
      A fast VHDL language server and analysis library written in Rust
      Rust
      68000Updated Feb 22, 2026Feb 22, 2026
    • OpenSTA

      Public
      OpenSTA Silimate fork
      C++
      55203Updated Feb 20, 2026Feb 20, 2026
    • silisizer

      Public
      Operator resize
      Verilog
      3101Updated Feb 19, 2026Feb 19, 2026
    • prunefl

      Public
      SystemVerilog file list pruner
      C++
      01600Updated Feb 18, 2026Feb 18, 2026
    • bounties

      Public
      Open-source silicon bounties
      0130Updated Feb 16, 2026Feb 16, 2026
    • abc

      Public
      ABC: System for Sequential Logic Synthesis and Formal Verification
      C
      724002Updated Feb 13, 2026Feb 13, 2026
    • rIC3

      Public
      Hardware Formal Verification Tool
      Rust
      22000Updated Feb 13, 2026Feb 13, 2026
    • A SystemVerilog language server based on the Slang parser and library.
      C++
      19000Updated Feb 13, 2026Feb 13, 2026
    • rtlmeter

      Public
      RTLMeter benchmark suite
      Verilog
      9000Updated Feb 13, 2026Feb 13, 2026
    • Parametrized suite of Verilog RTL benchmarks.
      Verilog
      4000Updated Feb 13, 2026Feb 13, 2026
    • SystemVerilog frontend for Yosys
      C++
      39000Updated Feb 13, 2026Feb 13, 2026
    • turtle

      Public
      TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025)
      Python
      7000Updated Feb 13, 2026Feb 13, 2026
    • wellen

      Public
      wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
      Rust
      19000Updated Feb 13, 2026Feb 13, 2026
    • Python
      17000Updated Feb 13, 2026Feb 13, 2026
    • HDL support for VS Code
      TypeScript
      84000Updated Feb 13, 2026Feb 13, 2026
    • verible

      Public
      Verible is a suite of SystemVerilog developer tools, including a parser, style-linter, formatter and language server
      C++
      272000Updated Feb 13, 2026Feb 13, 2026
    • verilator

      Public
      Verilator open-source SystemVerilog simulator and lint system
      SystemVerilog
      761000Updated Feb 13, 2026Feb 13, 2026
    • CULS

      Public
      GPU-based logic synthesis tool
      C++
      16000Updated Feb 13, 2026Feb 13, 2026
    • Copilot Chat extension for VS Code
      TypeScript
      1.7k000Updated Feb 13, 2026Feb 13, 2026
    • chimera

      Public
      A tool for synthesizing Verilog programs
      Verilog
      14100Updated Feb 13, 2026Feb 13, 2026
    • iverilog

      Public
      Icarus Verilog
      C++
      587000Updated Feb 13, 2026Feb 13, 2026
    • LEC - Logic Equivalence Checking - Formal Verification
      Verilog
      4000Updated Feb 12, 2026Feb 12, 2026
    • gtkwave

      Public
      GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files …
      C
      155000Updated Feb 6, 2026Feb 6, 2026
    • VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
      VHDL
      64000Updated Feb 3, 2026Feb 3, 2026
    • ibex

      Public
      Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
      SystemVerilog
      694000Updated Feb 3, 2026Feb 3, 2026