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[DRAFT][s4xbf16] JoinOp vectorization patch (Rebased) #25

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[DRAFT][s4xbf16] JoinOp vectorization patch (Rebased) #25

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c629b06
Bump to llvm/llvm-project@0aa5ba4 (#6266)
abulavin Mar 21, 2025
db4111f
Add heuristic for join to interleave every 2 elts
ggengnv Mar 20, 2025
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13 changes: 13 additions & 0 deletions lib/Conversion/TritonGPUToLLVM/ViewOpToLLVM.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -169,6 +169,19 @@ struct JoinOpConversion : public ConvertOpToLLVMPattern<JoinOp> {
assert(lhsVals.size() == rhsVals.size());
SmallVector<Value> joinedVals;
joinedVals.resize(lhsVals.size() * 2);

// Specifically for packed upcasting from 4b to 16b dtypes
// numContiguousValues cannot be too large, since the two outputs of
// inline_asm contain interleaved values OTOH, if numContiguousValues * 16b
// < 32b, then we'll need to rearrange 16b values in 32b registers. Hnece we
// set numContiguousValues to 2
auto inlineOp =
dyn_cast<ElementwiseInlineAsmOp>(op.getLhs().getDefiningOp());
if (inlineOp && inlineOp.getPackedElement() == 4 &&
dstTy.getElementTypeBitWidth() == 16) {
numContiguousValues = 2;
}

for (int i = 0; i < lhsVals.size(); i += numContiguousValues) {
for (int j = 0; j < numContiguousValues; j++) {
joinedVals[2 * i + j] = lhsVals[i + j];
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2 changes: 1 addition & 1 deletion python/src/llvm.cc
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Expand Up @@ -59,7 +59,7 @@ createTargetMachine(llvm::Module *module, std::string proc,
opt.MCOptions.AsmVerbose = true;
opt.MCOptions.PreserveAsmComments = true;
std::unique_ptr<llvm::TargetMachine> machine{target->createTargetMachine(
module->getTargetTriple(), proc, features, opt, llvm::Reloc::PIC_,
module->getTargetTriple().str(), proc, features, opt, llvm::Reloc::PIC_,
std::nullopt,
disableLLVMOpt ? llvm::CodeGenOptLevel::None
: llvm::CodeGenOptLevel::Aggressive)};
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