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ab74f2b
UCT/IB/MLX5: Track RC send PSN with path MTU
roiedanino Aug 24, 2026
31d155a
UCT/IB/MLX5: Avoid duplicate RC IOV traversal
roiedanino Aug 24, 2026
0290808
UCT/IB/MLX5: Compact send work queue layout
roiedanino Aug 24, 2026
119b4a4
UCT/IB/MLX5: Defer RC PSN masking to readers
roiedanino Aug 24, 2026
cb95c06
UCT/IB/MLX5: Initialize GGA path MTU for PSN tracking
roiedanino Aug 25, 2026
9c3c513
UCT/IB/MLX5: Centralize RC PSN update guard
roiedanino Aug 25, 2026
e76b940
UCT/IB/MLX5: Cache only path MTU shift
roiedanino Aug 26, 2026
a15642c
UCT/IB/MLX5: Move path MTU setup to control path
roiedanino Aug 26, 2026
2727b52
UCT/IB/MLX5: Align TXWQ reset assignments
roiedanino Aug 26, 2026
7d290d1
UCT/IB/MLX5: Order initialized send variables
roiedanino Aug 26, 2026
b917dc0
UCT/IB/MLX5: Use consistent RC QP checks
roiedanino Aug 26, 2026
34e3fa1
UCT/IB/MLX5: Align RC send assignments
roiedanino Aug 26, 2026
7f70643
UCT/IB/MLX5: Guard MMO opcode handling
roiedanino Aug 26, 2026
368df8e
UCT/IB/MLX5: Restore cached path MTU mask
roiedanino Aug 26, 2026
12d4983
UCT/IB/MLX5: Count zero-length sends as one packet
roiedanino Aug 26, 2026
c1d7701
UCT/IB/MLX5: Fix PSN tracking formatting
roiedanino Aug 26, 2026
e2eb81a
UCT/IB/MLX5: Address PSN tracking review comments
roiedanino Aug 26, 2026
a4e584d
UCT/IB/MLX5: Remove redundant IOV helper
roiedanino Aug 26, 2026
8f07fb4
UCT/IB/MLX5: Simplify data segment IOV helper
roiedanino Aug 26, 2026
d7d6abc
UCT/IB/MLX5: Handle zero-length PSN update explicitly
roiedanino Aug 27, 2026
d4eca25
UCT/IB/MLX5: Avoid zero-length PSN branch
roiedanino Aug 27, 2026
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1 change: 1 addition & 0 deletions src/uct/ib/mlx5/gga/gga_mlx5.c
Original file line number Diff line number Diff line change
Expand Up @@ -532,6 +532,7 @@ uct_gga_mlx5_ep_connect_to_ep_v2(uct_ep_h tl_ep,
return status;
}

uct_rc_mlx5_txwq_set_path_mtu(&ep->super.tx.wq, path_mtu);
ep->super.super.atomic_mr_offset = 0;
ep->super.super.flags |= UCT_RC_EP_FLAG_CONNECTED;
ep->super.super.flush_rkey =
Expand Down
26 changes: 21 additions & 5 deletions src/uct/ib/mlx5/ib_mlx5.c
Original file line number Diff line number Diff line change
Expand Up @@ -693,12 +693,15 @@ void uct_ib_mlx5_devx_uar_cleanup(uct_ib_mlx5_devx_uar_t *uar)

void uct_ib_mlx5_txwq_reset(uct_ib_mlx5_txwq_t *txwq)
{
txwq->curr = txwq->qstart;
txwq->sw_pi = 0;
txwq->prev_sw_pi = UINT16_MAX;
txwq->curr = txwq->qstart;
txwq->sw_pi = 0;
txwq->prev_sw_pi = UINT16_MAX;
txwq->next_wqe_psn = 0;
txwq->path_mtu_mask = 0;
txwq->path_mtu_shift = 0;
#if UCS_ENABLE_ASSERT
txwq->hw_ci = 0xFFFF;
txwq->flags = 0;
txwq->hw_ci = 0xFFFF;
txwq->flags = 0;
#endif
uct_ib_fence_info_init(&txwq->fi);
}
Expand All @@ -712,6 +715,16 @@ void uct_ib_mlx5_init_wq_buf(uct_ib_mlx5_txwq_t *txwq)
uct_ib_mlx5_set_ctrl_qpn_ds(uct_ib_mlx5_txwq_get_wqe(txwq, 0xffff), 0, 1);
}

static void
uct_ib_mlx5_txwq_vfs_show_next_wqe_psn(void *obj, ucs_string_buffer_t *strb,
void *arg_ptr, uint64_t arg_u64)
{
uct_ib_mlx5_txwq_t *txwq = arg_ptr;

ucs_string_buffer_appendf(
strb, "%u\n", uct_ib_mlx5_txwq_get_next_wqe_psn(txwq));
}

void uct_ib_mlx5_txwq_vfs_populate(uct_ib_mlx5_txwq_t *txwq, void *parent_obj)
{
ucs_vfs_obj_add_ro_file(parent_obj, ucs_vfs_show_primitive,
Expand All @@ -721,6 +734,9 @@ void uct_ib_mlx5_txwq_vfs_populate(uct_ib_mlx5_txwq_t *txwq, void *parent_obj)
UCS_VFS_TYPE_U16, "sw_pi");
ucs_vfs_obj_add_ro_file(parent_obj, ucs_vfs_show_primitive,
&txwq->prev_sw_pi, UCS_VFS_TYPE_U16, "prev_sw_pi");
ucs_vfs_obj_add_ro_file(parent_obj,
uct_ib_mlx5_txwq_vfs_show_next_wqe_psn, txwq, 0,
"next_wqe_psn");
ucs_vfs_obj_add_ro_file(parent_obj, ucs_vfs_show_primitive, &txwq->qstart,
UCS_VFS_TYPE_POINTER, "qstart");
ucs_vfs_obj_add_ro_file(parent_obj, ucs_vfs_show_primitive, &txwq->qend,
Expand Down
11 changes: 11 additions & 0 deletions src/uct/ib/mlx5/ib_mlx5.h
Original file line number Diff line number Diff line change
Expand Up @@ -686,13 +686,17 @@ typedef struct uct_ib_mlx5_txwq {
uct_ib_mlx5_qp_t super;

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Non-blocking (previously noted): next_wqe_psn is stored unmasked as uint32_t while the accessor masks to 24 bits.

uint16_t sw_pi; /* PI for next WQE */
uint16_t prev_sw_pi; /* PI where last WQE *started* */
uint32_t next_wqe_psn; /* 1st PSN of the next WQE to be
posted */
uct_ib_mlx5_mmio_reg_t *reg;
void *curr;
volatile uint32_t *dbrec;
void *qstart;
void *qend;
uint16_t bb_max;
uint16_t sig_pi; /* PI for last signaled WQE */
uint16_t path_mtu_mask; /* Path MTU in bytes - 1 */
uint8_t path_mtu_shift; /* log2(path MTU in bytes) */
#if UCS_ENABLE_ASSERT
uint16_t hw_ci; /* First BB index of last completed WQE */
uint8_t flags; /* Debug flags */
Expand All @@ -701,6 +705,13 @@ typedef struct uct_ib_mlx5_txwq {
} uct_ib_mlx5_txwq_t;


static UCS_F_ALWAYS_INLINE uint32_t

@jeynmann jeynmann Aug 26, 2026

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Minor: extract a small helper to centralize the 24-bit PSN masking, so future changes related to PSN would reuse this and make it easier to maintain.

Something like:

static UCS_F_ALWAYS_INLINE uint32_t
uct_ib_mlx5_psn24(uint32_t psn)
{
    return psn & UCS_MASK(24);
}

We might need this in later PRs.

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I would prefer to keep it inline for now and introduce a shared helper in the follow-up PR when it has multiple users.

uct_ib_mlx5_txwq_get_next_wqe_psn(const uct_ib_mlx5_txwq_t *txwq)
{
return txwq->next_wqe_psn & UCS_MASK(24);
}


/* Receive work-queue */
typedef struct uct_ib_mlx5_rxwq {
/* producer index. It updated when new receive wqe is posted */
Expand Down
18 changes: 13 additions & 5 deletions src/uct/ib/mlx5/ib_mlx5.inl
Original file line number Diff line number Diff line change
Expand Up @@ -509,10 +509,13 @@ uct_ib_mlx5_set_data_seg(struct mlx5_wqe_data_seg *dptr,
static UCS_F_ALWAYS_INLINE
size_t uct_ib_mlx5_set_data_seg_iov(uct_ib_mlx5_txwq_t *txwq,
struct mlx5_wqe_data_seg *dptr,
const uct_iov_t *iov, size_t iovcnt)
const uct_iov_t *iov, size_t iovcnt,
size_t *iov_length_p)
{
size_t wqe_size = 0;
size_t iov_length = 0;
size_t wqe_size = 0;
size_t iov_it;
size_t length;

for (iov_it = 0; iov_it < iovcnt; ++iov_it) {
if (!iov[iov_it].length) { /* Skip zero length WQE*/
Expand All @@ -522,13 +525,18 @@ size_t uct_ib_mlx5_set_data_seg_iov(uct_ib_mlx5_txwq_t *txwq,

/* place data into the buffer */
dptr = uct_ib_mlx5_txwq_wrap_any(txwq, dptr);
uct_ib_mlx5_set_data_seg(dptr, iov[iov_it].buffer,
uct_iov_get_length(iov + iov_it),
length = uct_iov_get_length(iov + iov_it);
uct_ib_mlx5_set_data_seg(dptr, iov[iov_it].buffer, length,
uct_ib_memh_get_lkey(iov[iov_it].memh));
wqe_size += sizeof(*dptr);
iov_length += length;
wqe_size += sizeof(*dptr);
++dptr;
}

if (iov_length_p != NULL) {
*iov_length_p = iov_length;
}

return wqe_size;
}

Expand Down
3 changes: 3 additions & 0 deletions src/uct/ib/mlx5/rc/rc_mlx5.h
Original file line number Diff line number Diff line change
Expand Up @@ -213,6 +213,9 @@ ucs_status_t uct_rc_mlx5_iface_create_qp(uct_rc_mlx5_iface_common_t *iface,
uct_ib_mlx5_txwq_t *txwq,
uct_ib_mlx5_qp_attr_t *attr);

void uct_rc_mlx5_txwq_set_path_mtu(uct_ib_mlx5_txwq_t *txwq,

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minor — misaligned continuation line. The enum ibv_mtu path_mtu line has one extra leading space; suggested:

Suggested change
void uct_rc_mlx5_txwq_set_path_mtu(uct_ib_mlx5_txwq_t *txwq,
void uct_rc_mlx5_txwq_set_path_mtu(uct_ib_mlx5_txwq_t *txwq,
enum ibv_mtu path_mtu);

The same misalignment exists in the definition in rc_mlx5_ep.c.

enum ibv_mtu path_mtu);

ucs_status_t
uct_rc_mlx5_ep_connect_qp(uct_rc_mlx5_iface_common_t *iface,
uct_ib_mlx5_qp_t *qp, uint32_t qp_num,
Expand Down
81 changes: 68 additions & 13 deletions src/uct/ib/mlx5/rc/rc_mlx5.inl
Original file line number Diff line number Diff line change
Expand Up @@ -452,6 +452,35 @@ uct_rc_mlx5_ep_fm_cq_update(uct_rc_mlx5_iface_common_t *iface,
return fm_ce_se;
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}

static UCS_F_ALWAYS_INLINE uint32_t
uct_rc_mlx5_num_packets(const uct_ib_mlx5_txwq_t *txwq,
size_t message_length)
{
ucs_assert(txwq->path_mtu_shift > 0);
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return (message_length + txwq->path_mtu_mask) >> txwq->path_mtu_shift;
}

static UCS_F_ALWAYS_INLINE void
uct_rc_mlx5_txwq_add_psn(uct_ib_mlx5_txwq_t *txwq, int qp_type,
uint32_t num_packets)
{
if (qp_type == IBV_QPT_RC) {
txwq->next_wqe_psn += num_packets;
}
}

static UCS_F_ALWAYS_INLINE void
uct_rc_mlx5_txwq_update_psn(uct_ib_mlx5_txwq_t *txwq, int qp_type,
size_t message_length)
{
if (qp_type == IBV_QPT_RC) {
uct_rc_mlx5_txwq_add_psn(txwq, qp_type,
uct_rc_mlx5_num_packets(txwq,
message_length));
}
}
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static UCS_F_ALWAYS_INLINE void
uct_rc_mlx5_common_post_send(uct_rc_mlx5_iface_common_t *iface, int qp_type,
uct_rc_txqp_t *txqp, uct_ib_mlx5_txwq_t *txwq,
Expand Down Expand Up @@ -532,6 +561,7 @@ static UCS_F_ALWAYS_INLINE void uct_rc_mlx5_txqp_inline_iov_post(
uct_rc_mlx5_common_post_send(iface, qp_type, txqp, txwq, MLX5_OPCODE_SEND,
0, fm_ce_se, dci_channel, wqe_size, 0,
INT_MAX, NULL);
uct_rc_mlx5_txwq_add_psn(txwq, qp_type, 1);
}

/*
Expand Down Expand Up @@ -627,6 +657,10 @@ uct_rc_mlx5_txqp_inline_post(uct_rc_mlx5_iface_common_t *iface, int qp_type,
uct_rc_mlx5_common_post_send(iface, qp_type, txqp, txwq, opcode, 0, fm_ce_se,
dci_channel, wqe_size, imm_val_be,
max_log_sge, NULL);
if (opcode != MLX5_OPCODE_NOP) {
/* Inline short operations always fit in one RC packet. */
uct_rc_mlx5_txwq_add_psn(txwq, qp_type, 1);
}
}

/*
Expand Down Expand Up @@ -707,6 +741,7 @@ uct_rc_mlx5_txqp_dptr_post(uct_rc_mlx5_iface_common_t *iface, int qp_type,
/* Data segment */
if (length == 0) {
wqe_size = ctrl_av_size + sizeof(*raddr);
uct_rc_mlx5_txwq_add_psn(txwq, qp_type, 1);
} else {
/* dptr cannot wrap, because ctrl+av could be either 2 or 4 segs */
dptr = uct_ib_mlx5_txwq_wrap_none(txwq, raddr + 1);
Expand Down Expand Up @@ -810,6 +845,7 @@ uct_rc_mlx5_txqp_dptr_post(uct_rc_mlx5_iface_common_t *iface, int qp_type,
(opcode_flags & UCT_RC_MLX5_OPCODE_MASK), opmod,
fm_ce_se, dci_channel, wqe_size, imm_val_be,
max_log_sge, log_sge);
uct_rc_mlx5_txwq_update_psn(txwq, qp_type, length);
}

static UCS_F_ALWAYS_INLINE
Expand All @@ -830,6 +866,7 @@ void uct_rc_mlx5_txqp_dptr_post_iov(uct_rc_mlx5_iface_common_t *iface, int qp_ty
struct mlx5_wqe_inl_data_seg *inl;
uct_rc_mlx5_hdr_t *rch;
unsigned wqe_size, inl_seg_size, ctrl_av_size;
size_t iov_length, message_length;
void *next_seg;
uint8_t opmod;
#if HAVE_MLX5_MMO
Expand All @@ -852,9 +889,6 @@ void uct_rc_mlx5_txqp_dptr_post_iov(uct_rc_mlx5_iface_common_t *iface, int qp_ty
inl_seg_size = ucs_align_up_pow2(sizeof(*inl) + sizeof(*rch) + am_hdr_len,
UCT_IB_MLX5_WQE_SEG_SIZE);

ucs_assert(uct_iov_total_length(iov, iovcnt) + sizeof(*rch) + am_hdr_len <=
iface->super.super.config.seg_size);

/* Inline segment with AM ID and header */
inl = next_seg;
inl->byte_count = htonl((sizeof(*rch) + am_hdr_len) | MLX5_INLINE_SEG);
Expand All @@ -866,9 +900,12 @@ void uct_rc_mlx5_txqp_dptr_post_iov(uct_rc_mlx5_iface_common_t *iface, int qp_ty
/* Data segment with payload */
dptr = (struct mlx5_wqe_data_seg *)((char *)inl + inl_seg_size);
wqe_size = ctrl_av_size + inl_seg_size +
uct_ib_mlx5_set_data_seg_iov(txwq, dptr, iov, iovcnt);
uct_ib_mlx5_set_data_seg_iov(
txwq, dptr, iov, iovcnt, &iov_length);
opmod = 0;
message_length = iov_length + sizeof(*rch) + am_hdr_len;

ucs_assert(message_length <= iface->super.super.config.seg_size);
ucs_assert(wqe_size <= UCT_IB_MLX5_MAX_SEND_WQE_SIZE);
break;

Expand All @@ -881,8 +918,10 @@ void uct_rc_mlx5_txqp_dptr_post_iov(uct_rc_mlx5_iface_common_t *iface, int qp_ty
inl->byte_count = htonl(sizeof(struct ibv_tmh) | MLX5_INLINE_SEG);
dptr = uct_ib_mlx5_txwq_wrap_exact(txwq, (char *)inl + inl_seg_size);
wqe_size = ctrl_av_size + inl_seg_size +
uct_ib_mlx5_set_data_seg_iov(txwq, dptr, iov, iovcnt);
uct_ib_mlx5_set_data_seg_iov(
txwq, dptr, iov, iovcnt, &iov_length);
opmod = 0;
message_length = iov_length + sizeof(struct ibv_tmh);

uct_rc_mlx5_fill_tmh((struct ibv_tmh*)(inl + 1), tag, app_ctx,
IBV_TMH_EAGER);
Expand All @@ -895,16 +934,16 @@ void uct_rc_mlx5_txqp_dptr_post_iov(uct_rc_mlx5_iface_common_t *iface, int qp_ty
/* Fall through */
case MLX5_OPCODE_RDMA_WRITE:
/* Set RDMA segment */
ucs_assert(uct_iov_total_length(iov, iovcnt) <= UCT_IB_MAX_MESSAGE_SIZE);

raddr = next_seg;
uct_ib_mlx5_ep_set_rdma_seg(raddr, remote_addr, rkey);

/* Data segment */
wqe_size = ctrl_av_size + sizeof(*raddr) +
uct_ib_mlx5_set_data_seg_iov(txwq, (void*)(raddr + 1),
iov, iovcnt);
opmod = 0;
wqe_size = ctrl_av_size + sizeof(*raddr) +
uct_ib_mlx5_set_data_seg_iov(
txwq, (void*)(raddr + 1), iov, iovcnt,
&message_length);
opmod = 0;
ucs_assert(message_length <= UCT_IB_MAX_MESSAGE_SIZE);
break;

#if HAVE_MLX5_MMO
Expand Down Expand Up @@ -938,8 +977,10 @@ void uct_rc_mlx5_txqp_dptr_post_iov(uct_rc_mlx5_iface_common_t *iface, int qp_ty
uct_ib_mlx5_set_data_seg(dptr /* scatter segment */,
dma_dst_buf, iov[0].length, dma_dst_key);

wqe_size = sizeof(*ctrl) + sizeof(*dma_seg) + (2 * sizeof(*dptr));
opmod = UCT_IB_MLX5_OPMOD_MMO_DMA;
wqe_size = sizeof(*ctrl) + sizeof(*dma_seg) +
(2 * sizeof(*dptr));
opmod = UCT_IB_MLX5_OPMOD_MMO_DMA;
message_length = 0;
break;
#endif
default:
Expand All @@ -950,6 +991,18 @@ void uct_rc_mlx5_txqp_dptr_post_iov(uct_rc_mlx5_iface_common_t *iface, int qp_ty
opcode_flags & UCT_RC_MLX5_OPCODE_MASK, opmod,
fm_ce_se, dci_channel, wqe_size, ib_imm_be,
max_log_sge, NULL);
#if HAVE_MLX5_MMO
if ((opcode_flags & UCT_RC_MLX5_OPCODE_MASK) == MLX5_OPCODE_MMO) {
return;
}
#endif
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uct_rc_mlx5_txwq_update_psn(txwq, qp_type, message_length);
if (opcode_flags == MLX5_OPCODE_RDMA_WRITE) {

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Zero-length RDMA_READ with message_length==0 would get update_psn(0)=0 PSN added because the special case only checks RDMA_WRITE, not RDMA_READ. This doesn't affect real paths (get_zcopy has a min length check and zero-length reads via dptr_post_iov don't occur), but it is a slight inconsistency with the dptr_post (bcopy) path which adds 1 for both READ and WRITE on the zero-length case.

/* opcode_flags is constant after inlining, so only zero-length
* PUT_ZCOPY gets the branchless one-PSN adjustment. */
uct_rc_mlx5_txwq_add_psn(txwq, qp_type, !message_length);
}
}

/*
Expand Down Expand Up @@ -1099,6 +1152,8 @@ uct_rc_mlx5_txqp_tag_inline_post(uct_rc_mlx5_iface_common_t *iface, int qp_type,
uct_rc_mlx5_common_post_send(iface, qp_type, txqp, txwq, opcode, 0,
fm_ce_se, dci_channel, wqe_size, imm_val_be,
INT_MAX, NULL);
/* Inline tag operations always fit in one RC packet. */
uct_rc_mlx5_txwq_add_psn(txwq, qp_type, 1);
}

static UCS_F_ALWAYS_INLINE void
Expand Down
19 changes: 18 additions & 1 deletion src/uct/ib/mlx5/rc/rc_mlx5_ep.c
Original file line number Diff line number Diff line change
Expand Up @@ -212,6 +212,7 @@ uct_rc_mlx5_base_ep_put_sgl_zcopy(uct_ep_h tl_ep, void * const *buffers,
uct_ib_mlx5_txwq_t *txwq = &ep->tx.wq;

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The DM short paths (put_short/am_short/am_short_iov via uct_rc_mlx5_common_ep_short_dm, and tag_eager_short) post an RC WQE but do not call uct_rc_mlx5_txwq_add_psn, so next_wqe_psn drifts when device memory is used (HAVE_IBV_DM and payload fits in DM segment). Unlike their inline counterparts (uct_rc_mlx5_txqp_inline_post, uct_rc_mlx5_txqp_inline_iov_post), the PSN is not advanced. This is non-blocking since the counter currently has no functional consumer beyond VFS/gtest, but if the intent is accurate PSN tracking, the DM path should also bump the PSN or be explicitly documented as excluded.

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The DM path is already covered indirectly through uct_rc_mlx5_common_txqp_bcopy_post() -> uct_rc_mlx5_txqp_dptr_post(), which updates PSN using hdr_len + iov_length. RC passes IBV_QPT_RC, while the DC update is compiled out, so an additional bump would double-count.

size_t total = 0;
struct mlx5_wqe_ctrl_seg *ctrl = NULL;
uint32_t num_packets = 0;
struct mlx5_wqe_raddr_seg *raddr;
struct mlx5_wqe_data_seg *dptr;
size_t wqe_size, i;
Expand Down Expand Up @@ -288,7 +289,8 @@ uct_rc_mlx5_base_ep_put_sgl_zcopy(uct_ep_h tl_ep, void * const *buffers,
curr = UCS_PTR_BYTE_OFFSET(ctrl, MLX5_SEND_WQE_BB);
curr = uct_ib_mlx5_txwq_wrap_exact(txwq, curr);
pi++;
total += lengths[i];
total += lengths[i];
num_packets += uct_rc_mlx5_num_packets(txwq, lengths[i]);
}

res_count = pi - 1 - txwq->prev_sw_pi;
Expand All @@ -299,6 +301,7 @@ uct_rc_mlx5_base_ep_put_sgl_zcopy(uct_ep_h tl_ep, void * const *buffers,

uct_rc_txqp_posted(&ep->super.txqp, &iface->super, res_count, 1);
uct_ib_mlx5_txwq_ring_doorbell(txwq, ctrl, txwq->sw_pi, 1);
uct_rc_mlx5_txwq_add_psn(txwq, IBV_QPT_RC, num_packets);

uct_rc_txqp_add_send_comp(&iface->super, &ep->super.txqp,
uct_rc_ep_send_op_completion_handler, comp, sn,
Expand Down Expand Up @@ -877,6 +880,18 @@ void uct_rc_mlx5_common_packet_dump(uct_base_iface_t *iface, uct_am_trace_type_t
valid_length, buffer, max);
}

void uct_rc_mlx5_txwq_set_path_mtu(uct_ib_mlx5_txwq_t *txwq,

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minor — misaligned continuation line. The enum ibv_mtu path_mtu line has one extra leading space, matching the misalignment in the declaration in rc_mlx5.h.

enum ibv_mtu path_mtu)
{
size_t mtu = uct_ib_mtu_value(path_mtu);

ucs_assert(mtu <= UINT16_MAX);
ucs_assert(ucs_is_pow2(mtu));

txwq->path_mtu_mask = mtu - 1;
txwq->path_mtu_shift = ucs_ilog2(mtu);
}

ucs_status_t
uct_rc_mlx5_ep_connect_qp(uct_rc_mlx5_iface_common_t *iface,
uct_ib_mlx5_qp_t *qp, uint32_t qp_num,
Expand Down Expand Up @@ -974,6 +989,8 @@ uct_rc_mlx5_ep_connect_to_ep_v2(uct_ep_h tl_ep,
return status;
}

uct_rc_mlx5_txwq_set_path_mtu(&ep->super.tx.wq, path_mtu);
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ep->super.super.atomic_mr_offset = uct_ib_md_atomic_offset(
rc_addr->atomic_mr_id);
ep->super.super.flags |= UCT_RC_EP_FLAG_CONNECTED;
Expand Down
6 changes: 3 additions & 3 deletions src/uct/ib/mlx5/ud/ud_mlx5.c
Original file line number Diff line number Diff line change
Expand Up @@ -320,9 +320,9 @@ static UCS_F_ALWAYS_INLINE ucs_status_t uct_ud_mlx5_ep_inline_iov_post(
/* set iov to dptr */
if (iovcnt > 0) {
wqe_size = ucs_align_up_pow2(wqe_size, UCT_IB_MLX5_WQE_SEG_SIZE);
wqe_size += uct_ib_mlx5_set_data_seg_iov(&iface->tx.wq,
UCS_PTR_BYTE_OFFSET(ctrl, wqe_size),
iov, iovcnt);
wqe_size += uct_ib_mlx5_set_data_seg_iov(
&iface->tx.wq, UCS_PTR_BYTE_OFFSET(ctrl, wqe_size), iov,
iovcnt, NULL);
}

uct_ud_mlx5_post_send(iface, ep, 0, ctrl, wqe_size, neth,
Expand Down
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