Merge pull request #582 from davideschiavone/alu_opcode_enum

🎨 changing to enumerator for alu opcodes

rtl/cv32e40p_alu.sv

@@ -30,7 +30,7 @@ module cv32e40p_alu import cv32e40p_pkg::*;
   input  logic                     clk,
   input  logic                     rst_n,
   input  logic                     enable_i,
-  input  logic [ALU_OP_WIDTH-1:0]  operator_i,
+  input  alu_opcode_e              operator_i,
   input  logic [31:0]              operand_a_i,
   input  logic [31:0]              operand_b_i,
   input  logic [31:0]              operand_c_i,

rtl/cv32e40p_core.sv

@@ -168,7 +168,7 @@ module cv32e40p_core import cv32e40p_apu_core_pkg::*;
 
   // ALU Control
   logic        alu_en_ex;
-  logic [ALU_OP_WIDTH-1:0] alu_operator_ex;
+  alu_opcode_e alu_operator_ex;
   logic [31:0] alu_operand_a_ex;
   logic [31:0] alu_operand_b_ex;
   logic [31:0] alu_operand_c_ex;
@@ -180,7 +180,7 @@ module cv32e40p_core import cv32e40p_apu_core_pkg::*;
   logic [ 1:0] alu_clpx_shift_ex;
 
   // Multiplier Control
-  logic [ 2:0] mult_operator_ex;
+  mul_opcode_e mult_operator_ex;
   logic [31:0] mult_operand_a_ex;
   logic [31:0] mult_operand_b_ex;
   logic [31:0] mult_operand_c_ex;
@@ -237,12 +237,12 @@ module cv32e40p_core import cv32e40p_apu_core_pkg::*;
 
   // CSR control
   logic        csr_access_ex;
-  logic [1:0]  csr_op_ex;
+  csr_opcode_e csr_op_ex;
   logic [23:0] mtvec, utvec;
   logic [1:0]  mtvec_mode;
   logic [1:0]  utvec_mode;
 
-  logic [1:0]  csr_op;
+  csr_opcode_e csr_op;
   csr_num_e    csr_addr;
   csr_num_e    csr_addr_int;
   logic [31:0] csr_rdata;

rtl/cv32e40p_cs_registers.sv

@@ -59,10 +59,10 @@ module cv32e40p_cs_registers import cv32e40p_pkg::*;
   input  logic            csr_mtvec_init_i,
 
   // Interface to registers (SRAM like)
-  input  csr_num_e                   csr_addr_i,
-  input  logic [31:0]                csr_wdata_i,
-  input  logic  [1:0]                csr_op_i,
-  output logic [31:0]                csr_rdata_o,
+  input  csr_num_e        csr_addr_i,
+  input  logic [31:0]     csr_wdata_i,
+  input  csr_opcode_e     csr_op_i,
+  output logic [31:0]     csr_rdata_o,
 
   output logic [2:0]         frm_o,
   input  logic [C_FFLAG-1:0] fflags_i,
@@ -1473,7 +1473,7 @@ end //PULP_SECURE
         end else if( (wcnt_gidx>2) && (wcnt_gidx<(NUM_MHPMCOUNTERS+3))) begin : gen_mhpmcounter
           // add +1 if any event is enabled and active
           assign mhpmcounter_write_increment[wcnt_gidx] = !mhpmcounter_write_lower[wcnt_gidx] &&
-                                                          !mhpmcounter_write_upper[wcnt_gidx] && 
+                                                          !mhpmcounter_write_upper[wcnt_gidx] &&
                                                           !mcountinhibit_q[wcnt_gidx] &&
                                                           |(hpm_events & mhpmevent_q[wcnt_gidx][NUM_HPM_EVENTS-1:0]);
         end else begin : gen_mhpmcounter_not_implemented
@@ -1482,7 +1482,7 @@ end //PULP_SECURE
       end else begin : gen_pulp_perf_counters
         // PULP PERF COUNTERS share all events in one register (not compliant with RISC-V)
         assign mhpmcounter_write_increment[wcnt_gidx] = !mhpmcounter_write_lower[wcnt_gidx] &&
-                                                        !mhpmcounter_write_upper[wcnt_gidx] && 
+                                                        !mhpmcounter_write_upper[wcnt_gidx] &&
                                                         !mcountinhibit_q[wcnt_gidx] &&
                                                         |(hpm_events & mhpmevent_q[wcnt_gidx][NUM_HPM_EVENTS-1:0]);
       end

rtl/cv32e40p_decoder.sv

@@ -76,7 +76,7 @@ module cv32e40p_decoder import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*;
 
   // ALU signals
   output logic        alu_en_o,                // ALU enable
-  output logic [ALU_OP_WIDTH-1:0] alu_operator_o, // ALU operation selection
+  output alu_opcode_e alu_operator_o, // ALU operation selection
   output logic [2:0]  alu_op_a_mux_sel_o,      // operand a selection: reg value, PC, immediate or zero
   output logic [2:0]  alu_op_b_mux_sel_o,      // operand b selection: reg value or immediate
   output logic [1:0]  alu_op_c_mux_sel_o,      // operand c selection: reg value or jump target
@@ -90,7 +90,7 @@ module cv32e40p_decoder import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*;
   output logic        is_subrot_o,
 
   // MUL related control signals
-  output logic [2:0]  mult_operator_o,         // Multiplication operation selection
+  output mul_opcode_e mult_operator_o,         // Multiplication operation selection
   output logic        mult_int_en_o,           // perform integer multiplication
   output logic        mult_dot_en_o,           // perform dot multiplication
   output logic [0:0]  mult_imm_mux_o,          // Multiplication immediate mux selector
@@ -120,7 +120,7 @@ module cv32e40p_decoder import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*;
   // CSR manipulation
   output logic        csr_access_o,            // access to CSR
   output logic        csr_status_o,            // access to xstatus CSR
-  output logic [1:0]  csr_op_o,                // operation to perform on CSR
+  output csr_opcode_e csr_op_o,                // operation to perform on CSR
   input  PrivLvl_t    current_priv_lvl_i,      // The current privilege level
 
   // LD/ST unit signals
@@ -161,7 +161,7 @@ module cv32e40p_decoder import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*;
   logic       csr_illegal;
   logic [1:0] ctrl_transfer_insn;
 
-  logic [1:0] csr_op;
+  csr_opcode_e csr_op;
 
   logic       alu_en;
   logic       mult_int_en;

rtl/cv32e40p_ex_stage.sv

@@ -42,7 +42,7 @@ module cv32e40p_ex_stage import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*
   input  logic        rst_n,
 
   // ALU signals from ID stage
-  input  logic [ALU_OP_WIDTH-1:0] alu_operator_i,
+  input  alu_opcode_e alu_operator_i,
   input  logic [31:0] alu_operand_a_i,
   input  logic [31:0] alu_operand_b_i,
   input  logic [31:0] alu_operand_c_i,
@@ -56,7 +56,7 @@ module cv32e40p_ex_stage import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*
   input  logic [ 1:0] alu_clpx_shift_i,
 
   // Multiplier signals
-  input  logic [ 2:0] mult_operator_i,
+  input  mul_opcode_e mult_operator_i,
   input  logic [31:0] mult_operand_a_i,
   input  logic [31:0] mult_operand_b_i,
   input  logic [31:0] mult_operand_c_i,

rtl/cv32e40p_id_stage.sv

@@ -109,20 +109,20 @@ module cv32e40p_id_stage import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*
 
     // ALU
     output logic        alu_en_ex_o,
-    output logic [ALU_OP_WIDTH-1:0] alu_operator_ex_o,
+    output alu_opcode_e alu_operator_ex_o,
     output logic        alu_is_clpx_ex_o,
     output logic        alu_is_subrot_ex_o,
     output logic [ 1:0] alu_clpx_shift_ex_o,
 
     // MUL
-    output logic [ 2:0] mult_operator_ex_o,
-    output logic [31:0] mult_operand_a_ex_o,
-    output logic [31:0] mult_operand_b_ex_o,
-    output logic [31:0] mult_operand_c_ex_o,
-    output logic        mult_en_ex_o,
-    output logic        mult_sel_subword_ex_o,
-    output logic [ 1:0] mult_signed_mode_ex_o,
-    output logic [ 4:0] mult_imm_ex_o,
+    output mul_opcode_e  mult_operator_ex_o,
+    output logic [31:0]  mult_operand_a_ex_o,
+    output logic [31:0]  mult_operand_b_ex_o,
+    output logic [31:0]  mult_operand_c_ex_o,
+    output logic         mult_en_ex_o,
+    output logic         mult_sel_subword_ex_o,
+    output logic [ 1:0]  mult_signed_mode_ex_o,
+    output logic [ 4:0]  mult_imm_ex_o,
 
     output logic [31:0] mult_dot_op_a_ex_o,
     output logic [31:0] mult_dot_op_b_ex_o,
@@ -152,7 +152,7 @@ module cv32e40p_id_stage import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*
 
     // CSR ID/EX
     output logic        csr_access_ex_o,
-    output logic [1:0]  csr_op_ex_o,
+    output csr_opcode_e csr_op_ex_o,
     input  PrivLvl_t    current_priv_lvl_i,
     output logic        csr_irq_sec_o,
     output logic [5:0]  csr_cause_o,
@@ -350,7 +350,7 @@ module cv32e40p_id_stage import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*
 
   // ALU Control
   logic        alu_en;
-  logic [ALU_OP_WIDTH-1:0] alu_operator;
+  alu_opcode_e alu_operator;
   logic [2:0]  alu_op_a_mux_sel;
   logic [2:0]  alu_op_b_mux_sel;
   logic [1:0]  alu_op_c_mux_sel;
@@ -361,7 +361,7 @@ module cv32e40p_id_stage import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*
   logic [1:0]  ctrl_transfer_target_mux_sel;
 
   // Multiplier Control
-  logic [2:0]  mult_operator;    // multiplication operation selection
+  mul_opcode_e mult_operator;    // multiplication operation selection
   logic        mult_en;          // multiplication is used instead of ALU
   logic        mult_int_en;      // use integer multiplier
   logic        mult_sel_subword; // Select a subword when doing multiplications
@@ -421,7 +421,7 @@ module cv32e40p_id_stage import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*
 
   // CSR control
   logic        csr_access;
-  logic [1:0]  csr_op;
+  csr_opcode_e csr_op;
   logic        csr_status;
 
   logic        prepost_useincr;
@@ -1429,7 +1429,7 @@ module cv32e40p_id_stage import cv32e40p_pkg::*; import cv32e40p_apu_core_pkg::*
       alu_is_clpx_ex_o            <= 1'b0;
       alu_is_subrot_ex_o          <= 1'b0;
 
-      mult_operator_ex_o          <= '0;
+      mult_operator_ex_o          <= MUL_MAC32;
       mult_operand_a_ex_o         <= '0;
       mult_operand_b_ex_o         <= '0;
       mult_operand_c_ex_o         <= '0;

rtl/cv32e40p_mult.sv

@@ -23,13 +23,13 @@
 //                                                                            //
 ////////////////////////////////////////////////////////////////////////////////
 
-module cv32e40p_mult
+module cv32e40p_mult import cv32e40p_pkg::*;
 (
   input  logic        clk,
   input  logic        rst_n,
 
   input  logic        enable_i,
-  input  logic [ 2:0] operator_i,
+  input  mul_opcode_e operator_i,
 
   // integer and short multiplier
   input  logic        short_subword_i,