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cpu: aarch64: batch_normalization : Expand ARM SVE support in jit_uni_batch_normalization #1918

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@nikhilfujitsu nikhilfujitsu commented May 15, 2024

Description

This commit enhances the existing ARM SVE support in jit_uni_batch_normalization to include additional vector length compatibility. The changes made are for implementation of different ARM SVE vector length.

Major Code changes:

Updated the block size definition to accommodate other SVE vector length.
Added 'OR' and 'AND' conditions to extend support for other SVE vector.
Predicate registers are set according to isa vector length.
ldr and str instructions are replaced by ld1w and st1w respectively. For appropriate load and strore operation considering isa vector length.

Checklist

General
[✓] Do all unit and benchdnn tests (make test and make test_benchdnn_*) pass locally for each commit? Yes
Test output is same with and without this commit.

make test output:
99% tests passed, 1 tests failed out of 103

Total Test time (real) = 36.37 sec

The following tests FAILED:
102 - test_graph_unit_cpu (Failed)
Errors while running CTest
Output from these tests are in: /home/nikhil/TEST/oneDNN/build/Testing/Temporary/LastTest.log
Use "--rerun-failed --output-on-failure" to re-run the failed cases verbosely.
make: *** [Makefile:71: test] Error 8

make test_benchdnn_* output:
make: *** No rule to make target 'test_benchdnn_*'. Stop.

make test_benchdnn_bnorm_ci_cpu/fast output.
tests:4445 passed:1232 skipped:2989 mistrusted:224 unimplemented:0 invalid_arguments:0 failed:0 listed:0

cpu: aarch64: Expand ARM SVE support in jit_uni_batch_normalization

Added sve_256 in the implementation list
Update jit_uni_batch_normalization.cpp
Updated the block size definition to accommodate different ISAs.
Added 'OR' conditions to extend support for additonal block_size.
Predicate registers are set according to isa vector length.
ldr and str instruction changed to ldw1 and stw1 respectively. To support load and store operations as per ISA.
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@mgouicem mgouicem left a comment

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Thank you for the contribution. Tagging @jondea

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@jondea jondea left a comment

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Thank you for the contribution, we really appreciate your work on vlen 256. I just have a few comments about whether it could be more general. If it works for an SVE vlen of 256 and 512, why not any length? Then you could remove any hard coded vlen variables, and there could be a single implementation.

@vpirogov vpirogov added this to the v3.6 milestone May 21, 2024
@abhijain1204fujitsu
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@vpirogov , Hello
Can you please merge the PR as the changes are approved
In case anything is required from our end, do let us know.

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5 participants