FPGA: Add new sample SVD

[KevinUTAT]

Description

Adding a new FPGA reference design Singular Value Decomposition.

Testing

Running reg-tests, will update test links once finished.

Checklist

Administrative

• Review sample design with the appropriate Domain Expert:
• If you have any new dependencies/binaries, inform the oneAPI Code Samples Project Manager

Code Development

• Implement coding guidelines and ensure code quality. see wiki for details
• Adhere to readme template
• Enforce format via clang-format config file
• Adhere to sample.json specification. https://github.com/oneapi-src/oneAPI-samples/wiki/sample-json-specification
• Ensure/create CI test configurations for sample (ciTests field) https://github.com/oneapi-src/oneAPI-samples/wiki/sample-json-ci-test-object
• Run jsonlint on sample.json to verify json syntax. www.jsonlint.com

Security and Legal

• OSPDT Approval (see Project Manager for assistance)
• Compile using the following compiler flags and fix any warnings, the falgs are: "/Wall -Wformat-security -Werror=format-security"
• Bandit Scans (Python only)
• Virus scan

Review

• Review DPC++ code with Paul Peterseon. (GitHub User: pmpeter1)
• Review readme with Tom Lenth(@tomlenth) and/or Project Manager
• Tested using Dev Cloud when applicable

[jimmytwei]

Adding @pmpeter1 and @tomlenth per request by @KevinUTAT

[tomlenth]

Looks pretty solid. thx!

[yuguen-intel]

Did you get the chance to compute estimated performance to compare with what you obtained in HW?

[yuguen-intel]

Run this sample on N6001 to update the readme from DE10 to N6001 as we moved to this board.

[yuguen-intel]

PCA? I guess you meant SVD? Or maybe you didn't mean to add this file?

[KevinUTAT]

I copy the golden PCA to obtain the eigen values for reference, so it technically is PCA