[nrf fromlist] drivers: serial: nrfx_uarte: Add mode with TIMER byte counting #3033
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| { | ||
| nrf_timer_task_trigger(timer, nrf_timer_capture_task_get(UARTE_TIMER_CAPTURE_CH)); | ||
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| nrf_barrier_w(); |
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I think it might not be needed - accesses (task trigger and register read) toward same bus slave (peripheral) should never be re-ordered
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it is actually needed for VPR. zephyrproject-rtos/zephyr@c9bbc5a
drivers/serial/uart_nrfx_uarte.c
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| /* Set past value to ensure that event will not expire after clearing but | ||
| * before setting the new value. | ||
| */ | ||
| nrf_timer_cc_set(cfg->timer_regs, UARTE_TIMER_USR_CNT_CH, cbwt_data->cc_usr - 10); |
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no risk of underflow on cbwt_data->cc_usr - 10?
Maybe would be good to replace 10 with define, so it is more readable why 10 specifically?
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I changed it to -1, i did not add any magic number as -1 is self explanatory as past value.
drivers/serial/uart_nrfx_uarte.c
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| uint8_t *dma_buf; | ||
| int ret = 0; | ||
| if (!IS_CBWT(dev)) { | ||
| uint8_t *dma_buf; |
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nit: declaring dma_buf as void * could maybe help avoiding casting to void** below
west.yml
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| @@ -200,7 +200,7 @@ manifest: | |||
| groups: | |||
| - hal | |||
| - name: hal_nordic | |||
| revision: 71308dc6d8c021887ce5d98a36cafe9517375a91 | |||
| revision: pull/306/head | |||
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is it really needed? I believe MDK accesses are already utilized instead of HAL functions. Maybe _tx/rx_macnt_set functions would need to be converted to MDK accesses as well to get rid of the dependency.
Alternatively we could wait for nrfx release
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replaced usage with MDK register access. It can later on be updated to use hal from nrfx 3.13.
Timer property indicates which TIMER instance should be used for byte counting. If timer property is present then given instance is using TIMER to count received bytes. Upstream PR #: 92767 Signed-off-by: Krzysztof Chruściński <[email protected]>
Add reporting about the test progress. Test lasts few seconds and progress report helps to see if test stuck or how it is progressing. Upstream PR #: 92767 Signed-off-by: Krzysztof Chruściński <[email protected]>
Extend test with a mode where HWFC is off and receiver is providing buffers on time. In that case receiver should be able to continuously receive data without losing any byte (even without HWFC). Additionally, TX data is chopped to verify that receiver does not loose bytes when new TX data collides with detected RX timeout. Upstream PR #: 92767 Signed-off-by: Krzysztof Chruściński <[email protected]>
… for nrf54l Add timer property to the uart device under test. Add zephyr,pm-device-runtime-auto to the uart device under test. Upstream PR #: 92767 Signed-off-by: Krzysztof Chruściński <[email protected]>
…nfiguration Add workaround timer to instances that are used for reception in the test. Upstream PR #: 92767 Signed-off-by: Krzysztof Chruściński <[email protected]>
…andling Stress test is executed on CPUs with slow clock (16MHz). Handling of test data in UART_RX_RDY event is optimized to reduce time spent in the interrupt context. Since payload is always a decrementing sequence, fixed array is used to compare memory which allows to use standard memcmp instead of byte by byte comparison. Upstream PR #: 92767 Signed-off-by: Krzysztof Chruściński <[email protected]>
Rearrange code to prepare for upcoming extension that adds special receive mode. Upstream PR #: 92767 Signed-off-by: Krzysztof Chruściński <[email protected]>
…counting Add mode to be used on UARTE with frame timeout which is using a bounce buffers and TIMER to count bytes. This mode shall be used to reliably receive data without HWFC as frame timeout approach is not 100% reliable because it can loose or corrupt a byte when new byte arrives after frame timeout is detected but before it is fully handled. This mode is similar to the one enabled with CONFIG_UART_x_NRF_HW_ASYNC but additional bounce buffers are used and UARTE is receiving data to internal buffers and copies data to the user buffer. Legacy apporach cannot be used because in new SoC DMA attempts to copy data in words so when byte is received it stays in the DMA internal buffer until 4 bytes are received or end of transfer happens then internal DMA buffer is flushed. Upstream PR #: 92767 Signed-off-by: Krzysztof Chruściński <[email protected]>
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Upstream PR 92767