Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Need to make a bunch of changes because Verilator does not support some features of SystemVerilog.
When I got this running, the simulation was about 100x slower than
vvp
. Looking at the logs, Verilator appears to be spending a lot of work waiting for delays.Knowing that Verilator was designed to handle purely cycle-based designs, I guess that the extensive use of delays throughout the project was hitting a pathological case. So I removed all delays.
But when I finally got it to run far enough, the simulation was not working. I guess maybe removing all timings broke it, but could very well have other problems.
I am publishing my work here in case anyone else also wanted to pursue this.