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LeoSoC

License UPRJ_CI Caravel Build

This is a simple SoC with the following:

  • 1 LeoRV32 Core (RV32I)
  • 8 kB Work RAM
  • 8 kB Video RAM (can also be used as Work RAM)
  • SVGA Core (800 x 600, 40 MHz)
    • Resolution decreased to 100 x 75 pixel
    • 1 Byte per Pixel with direct color format (BBGGGRRR)
  • UART
    • 9600 baud fixed at 40 MHz
  • Blink
    • Simple output to blink an LED

Address Layout

Peripheral Address
WRAM_BASE 0x000000
VRAM_BASE 0x010000
UART_BASE 0x0A0000
BLINK_BASE 0x0F0000

Layout

leosoc.png