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1. sobel-edge-detection-fpga sobel-edge-detection-fpga Public

   A convolution-based Sobel edge detection system on the Nexys A7 FPGA.

   Verilog 1

2. object-recognition-turret object-recognition-turret Public

   Object Recognition Turret

   Python 1

3. gate-level-alu gate-level-alu Public

   A 4-bit Arithmetic Logic Unit (ALU) built at gate level abstraction and implemented on the Basys 3 Artix-7 FPGA.

   Verilog 1

4. osmosis osmosis Public

   A digital hardware implementation of a cell membrane simulation game designed for an Artix-7 FPGA using Verilog.

   Verilog 1

5. hhds hhds Public

   Forked from masc-ucsc/hhds

   Hardware Hierarchical Dynamic Structures

   C++

6. livehd livehd Public

   Forked from masc-ucsc/livehd

   Live Hardware Development (LiveHD), a productive infrastructure for Synthesis and Simulation

   FIRRTL