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This repository was archived by the owner on Oct 30, 2021. It is now read-only.

Commit 177ddd1

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Fix dtso after messed up merge
1 parent e1a01ac commit 177ddd1

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-195
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2 files changed

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overlay.dtbo

-2.87 KB
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overlay.dtso

Lines changed: 0 additions & 195 deletions
Original file line numberDiff line numberDiff line change
@@ -5,11 +5,7 @@
55

66
fragment@0 {
77
target-path = "/soc/base-fpga-region";
8-
<<<<<<< HEAD
98
#address-cells = <0x1>;
10-
=======
11-
#address-cells = <0x1>;
12-
>>>>>>> small
139
#size-cells = <0x1>;
1410

1511
__overlay__ {
@@ -19,160 +15,22 @@
1915
fpga-bridges = <0xffffffff 0xffffffff>;
2016
ranges = <0x0 0x0 0xc0000000 0x20000000 0x1 0x0 0xff200000 0x200000>;
2117

22-
<<<<<<< HEAD
23-
clk_0 {
24-
compatible = "fixed-clock";
25-
#clock-cells = <0x0>;
26-
clock-frequency = <0x2faf080>;
27-
linux,phandle = <0x1>;
28-
phandle = <0x1>;
29-
};
30-
31-
serial@0x100002000 {
32-
compatible = "altr,juart-16.0", "altr,juart-1.0";
33-
reg = <0x1 0x2000 0x8>;
34-
interrupt-parent = <0xffffffff>;
35-
interrupts = <0x0 0x2a 0x4>;
36-
clocks = <0x1>;
37-
linux,phandle = <0x3>;
38-
phandle = <0x3>;
39-
};
40-
41-
gpio@0x100003000 {
42-
compatible = "altr,pio-16.0", "altr,pio-1.0";
43-
reg = <0x1 0x3000 0x10>;
44-
clocks = <0x1>;
45-
altr,gpio-bank-width = <0x8>;
46-
resetvalue = <0xff>;
47-
#gpio-cells = <0x2>;
48-
gpio-controller;
49-
linux,phandle = <0x2>;
50-
phandle = <0x2>;
51-
};
52-
53-
gpio@0x100004000 {
54-
compatible = "altr,pio-16.0", "altr,pio-1.0";
55-
reg = <0x1 0x4000 0x10>;
56-
interrupt-parent = <0xffffffff>;
57-
interrupts = <0x0 0x28 0x1>;
58-
clocks = <0x1>;
59-
altr,gpio-bank-width = <0x4>;
60-
altr,interrupt-type = <0x3>;
61-
altr,interrupt_type = <0x3>;
62-
edge_type = <0x2>;
63-
level_trigger = <0x0>;
64-
resetvalue = <0x0>;
65-
#gpio-cells = <0x2>;
66-
gpio-controller;
67-
linux,phandle = <0x7>;
68-
phandle = <0x7>;
69-
};
70-
71-
gpio@0x100005000 {
72-
compatible = "altr,pio-16.0", "altr,pio-1.0";
73-
reg = <0x1 0x5000 0x10>;
74-
interrupt-parent = <0xffffffff>;
75-
interrupts = <0x0 0x29 0x1>;
76-
clocks = <0xffffffff>;
77-
altr,gpio-bank-width = <0x2>;
78-
altr,interrupt-type = <0x2>;
79-
altr,interrupt_type = <0x2>;
80-
edge_type = <0x1>;
81-
level_trigger = <0x0>;
82-
resetvalue = <0x0>;
83-
#gpio-cells = <0x2>;
84-
gpio-controller;
85-
linux,phandle = <0x8>;
86-
phandle = <0x8>;
87-
};
88-
89-
miner@0x100006000 {
90-
compatible = "cyr,miner-1.1", "dev,miner";
91-
reg = <0x00000001 0x00006000 0x00000080>;
92-
interrupt-parent = <0xffffffff>;
93-
interrupts = <0x0 0x2a 0x4>;
94-
clocks = <0xffffffff>;
95-
// linux,phandle = <0x9>;
96-
// phandle = <0x9>;
97-
};
98-
99-
ov-leds {
100-
compatible = "gpio-leds";
101-
102-
fpga0 {
103-
label = "fpga_led0";
104-
gpios = <0x2 0x0 0x0>;
105-
};
106-
107-
fpga1 {
108-
label = "fpga_led1";
109-
gpios = <0x2 0x1 0x0>;
110-
};
111-
112-
fpga2 {
113-
label = "fpga_led2";
114-
gpios = <0x2 0x2 0x0>;
115-
};
116-
117-
fpga3 {
118-
label = "fpga_led3";
119-
gpios = <0x2 0x3 0x0>;
120-
};
121-
122-
fpga4 {
123-
label = "fpga_led4";
124-
gpios = <0x2 0x4 0x0>;
125-
};
126-
127-
fpga5 {
128-
label = "fpga_led5";
129-
gpios = <0x2 0x5 0x0>;
130-
};
131-
132-
fpga6 {
133-
label = "fpga_led6";
134-
gpios = <0x2 0x6 0x0>;
135-
};
136-
137-
fpga7 {
138-
label = "fpga_led7";
139-
gpios = <0x2 0x7 0x0>;
140-
};
141-
};
142-
=======
14318
miner@100006000 {
14419
compatible = "cyr,miner-1.1", "dev,miner";
14520
reg = <0x00000001 0x00006000 0x00000080>;
14621
interrupt-parent = <0xffffffff>;
14722
interrupts = <0x0 0x28 0x4>;
14823
clocks = <0xffffffff>;
14924
};
150-
>>>>>>> small
15125
};
15226
};
15327

15428
__symbols__ {
155-
<<<<<<< HEAD
156-
clk_0 = "/fragment@0/__overlay__/clk_0";
157-
jtag_uart = "/fragment@0/__overlay__/serial@0x100002000";
158-
led_pio = "/fragment@0/__overlay__/gpio@0x100003000";
159-
dipsw_pio = "/fragment@0/__overlay__/gpio@0x100004000";
160-
button_pio = "/fragment@0/__overlay__/gpio@0x100005000";
161-
miner_0 = "/fragment@0/__overlay__/miner@0x100006000";
162-
};
163-
164-
__fixups__ {
165-
fpga_bridge0 = "/fragment@0/__overlay__:fpga-bridges:0";
166-
fpga_bridge1 = "/fragment@0/__overlay__:fpga-bridges:4";
167-
intc = "/fragment@0/__overlay__/serial@0x100002000:interrupt-parent:0", "/fragment@0/__overlay__/gpio@0x100004000:interrupt-parent:0", "/fragment@0/__overlay__/gpio@0x100005000:interrupt-parent:0", "/fragment@0/__overlay__/miner@0x100006000:interrupt-parent:0";
168-
osc1 = "/fragment@0/__overlay__/gpio@0x100005000:clocks:0";
169-
=======
17029
miner_0 = "/fragment@0/__overlay__/miner@100006000";
17130
};
17231

17332
__fixups__ {
17433
intc = "/fragment@0/__overlay__/miner@100006000:interrupt-parent:0";
175-
>>>>>>> small
17634
};
17735

17836
__local_fixups__ {
@@ -181,62 +39,9 @@
18139

18240
__overlay__ {
18341

184-
<<<<<<< HEAD
185-
serial@0x100002000 {
186-
clocks = <0x0>;
187-
};
188-
189-
gpio@0x100003000 {
190-
clocks = <0x0>;
191-
};
192-
193-
gpio@0x100004000 {
194-
clocks = <0x0>;
195-
};
196-
197-
miner@0x100006000 {
198-
clocks = <0x0>;
199-
};
200-
201-
ov-leds {
202-
203-
fpga0 {
204-
gpios = <0x0>;
205-
};
206-
207-
fpga1 {
208-
gpios = <0x0>;
209-
};
210-
211-
fpga2 {
212-
gpios = <0x0>;
213-
};
214-
215-
fpga3 {
216-
gpios = <0x0>;
217-
};
218-
219-
fpga4 {
220-
gpios = <0x0>;
221-
};
222-
223-
fpga5 {
224-
gpios = <0x0>;
225-
};
226-
227-
fpga6 {
228-
gpios = <0x0>;
229-
};
230-
231-
fpga7 {
232-
gpios = <0x0>;
233-
};
234-
};
235-
=======
23642
miner@100006000 {
23743
clocks = <0x0>;
23844
};
239-
>>>>>>> small
24045
};
24146
};
24247
};

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