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Commit e1a01ac

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jean-m-cyrjean-m-cyr
committed
Merge branch 'small'
- 90MHz miner clock
2 parents 84182a0 + 3257bea commit e1a01ac

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14 files changed

+53995
-58805
lines changed

14 files changed

+53995
-58805
lines changed

‎DE10_NANO_SOC_GHRD.qsf‎

Lines changed: 1 addition & 29 deletions
Original file line numberDiff line numberDiff line change
@@ -24,28 +24,14 @@ set_location_assignment PIN_V11 -to FPGA_CLK1_50
2424
#============================================================
2525
# KEY
2626
#============================================================
27-
set_location_assignment PIN_AH17 -to KEY[0]
28-
set_location_assignment PIN_AH16 -to KEY[1]
2927

3028
#============================================================
3129
# LED
3230
#============================================================
33-
set_location_assignment PIN_W15 -to LED[0]
34-
set_location_assignment PIN_AA24 -to LED[1]
35-
set_location_assignment PIN_V16 -to LED[2]
36-
set_location_assignment PIN_V15 -to LED[3]
37-
set_location_assignment PIN_AF26 -to LED[4]
38-
set_location_assignment PIN_AE26 -to LED[5]
39-
set_location_assignment PIN_Y16 -to LED[6]
40-
set_location_assignment PIN_AA23 -to LED[7]
4131

4232
#============================================================
4333
# SW
4434
#============================================================
45-
set_location_assignment PIN_Y24 -to SW[0]
46-
set_location_assignment PIN_W24 -to SW[1]
47-
set_location_assignment PIN_W21 -to SW[2]
48-
set_location_assignment PIN_W20 -to SW[3]
4935

5036
#============================================================
5137
# End of pin assignments by Terasic System Builder
@@ -184,20 +170,6 @@ set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DATA[7]
184170
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_DIR
185171
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_NXT
186172
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to HPS_USB_STP
187-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[0]
188-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to KEY[1]
189-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[0]
190-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[1]
191-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[2]
192-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[3]
193-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[4]
194-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[5]
195-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[6]
196-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to LED[7]
197-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[0]
198-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[1]
199-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[2]
200-
set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to SW[3]
201173
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0
202174
set_instance_assignment -name OUTPUT_TERMINATION "SERIES 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[0] -tag __hps_sdram_p0
203175
set_instance_assignment -name INPUT_TERMINATION "PARALLEL 50 OHM WITH CALIBRATION" -to HPS_DDR3_DQ[1] -tag __hps_sdram_p0
@@ -399,7 +371,7 @@ set_instance_assignment -name GLOBAL_SIGNAL OFF -to u0|hps_0|hps_io|border|hps_s
399371
set_instance_assignment -name ENABLE_BENEFICIAL_SKEW_OPTIMIZATION_FOR_NON_GLOBAL_CLOCKS ON -to u0|hps_0|hps_io|border|hps_sdram_inst -tag __hps_sdram_p0
400372
set_instance_assignment -name PLL_COMPENSATION_MODE DIRECT -to u0|hps_0|hps_io|border|hps_sdram_inst|pll0|fbout -tag __hps_sdram_p0
401373
set_global_assignment -name TIMING_ANALYZER_MULTICORNER_ANALYSIS ON
402-
set_global_assignment -name NUM_PARALLEL_PROCESSORS 8
374+
set_global_assignment -name NUM_PARALLEL_PROCESSORS ALL
403375
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE PERFORMANCE"
404376
set_global_assignment -name VERILOG_FILE DE10_NANO_SOC_GHRD.v
405377
set_global_assignment -name SDC_FILE DE10_NANO_SOC_GHRD.sdc

‎DE10_NANO_SOC_GHRD.v‎

Lines changed: 3 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -69,16 +69,7 @@ module DE10_NANO_SOC_GHRD(
6969
inout [ 7: 0] HPS_USB_DATA,
7070
input HPS_USB_DIR,
7171
input HPS_USB_NXT,
72-
output HPS_USB_STP,
73-
74-
//////////// KEY //////////
75-
input [ 1: 0] KEY,
76-
77-
//////////// LED //////////
78-
output [ 7: 0] LED,
79-
80-
//////////// SW //////////
81-
input [ 3: 0] SW
72+
output HPS_USB_STP
8273

8374
);
8475

@@ -93,10 +84,7 @@ wire [2: 0] hps_reset_req;
9384
wire hps_cold_reset;
9485
wire hps_warm_reset;
9586
wire hps_debug_reset;
96-
wire [6: 0] fpga_led_internal;
97-
wire fpga_bsy;
9887

99-
assign LED[7: 1] = fpga_led_internal;
10088

10189
//=======================================================
10290
// Structural coding
@@ -177,34 +165,13 @@ soc_system u0(
177165
.hps_0_hps_io_hps_io_gpio_inst_GPIO40(HPS_LTC_GPIO), // .hps_io_gpio_inst_GPIO40
178166
.hps_0_hps_io_hps_io_gpio_inst_GPIO53(HPS_LED), // .hps_io_gpio_inst_GPIO53
179167
.hps_0_hps_io_hps_io_gpio_inst_GPIO54(HPS_KEY), // .hps_io_gpio_inst_GPIO54
180-
.hps_0_hps_io_hps_io_gpio_inst_GPIO61(HPS_GSENSOR_INT), // .hps_io_gpio_inst_GPIO61
181-
//FPGA Partion
182-
.led_pio_external_connection_export(fpga_led_internal), // led_pio_external_connection.export
183-
.dipsw_pio_external_connection_export(SW), // dipsw_pio_external_connection.export
184-
.button_pio_external_connection_export(fpga_debounced_buttons),
168+
.hps_0_hps_io_hps_io_gpio_inst_GPIO61(HPS_GSENSOR_INT),
185169
// button_pio_external_connection.export
186170

187171
.hps_0_h2f_reset_reset_n(hps_fpga_reset_n), // hps_0_h2f_reset.reset_n
188172
.hps_0_f2h_cold_reset_req_reset_n(~hps_cold_reset), // hps_0_f2h_cold_reset_req.reset_n
189173
.hps_0_f2h_debug_reset_req_reset_n(~hps_debug_reset), // hps_0_f2h_debug_reset_req.reset_n
190-
.hps_0_f2h_warm_reset_req_reset_n(~hps_warm_reset), // hps_0_f2h_warm_reset_req.reset_n
191-
192-
.miner_0_conduit_bsy(fpga_bsy)
193-
);
194-
195-
assign LED[0] = fpga_bsy;
196-
197-
// Debounce logic to clean out glitches within 1ms
198-
debounce #(
199-
.WIDTH(2),
200-
.POLARITY("LOW"),
201-
.TIMEOUT(50000), // at 50Mhz this is a debounce time of 1ms
202-
.TIMEOUT_WIDTH(16) // ceil(log2(TIMEOUT))
203-
) inst (
204-
.clk(FPGA_CLK1_50),
205-
.reset_n(hps_fpga_reset_n),
206-
.data_in(KEY),
207-
.data_out(fpga_debounced_buttons)
174+
.hps_0_f2h_warm_reset_req_reset_n(~hps_warm_reset)
208175
);
209176

210177
altera_edge_detector #(

‎hps_isw_handoff/soc_system_hps_0/id‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,3 @@
11
Do not change the content of this file
2-
MD5 : 05f129a584ff7fc8ea0c2375bf10f748
3-
CRC32 : 0x04642965
2+
MD5 : 55dd734a9ebc18050b313426aa26d8da
3+
CRC32 : 0x96CACC6B

‎miner_hw.tcl‎

Lines changed: 2 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1,11 +1,11 @@
11
# TCL File Generated by Component Editor 18.1
2-
# Sat Aug 15 19:19:12 EDT 2020
2+
# Sat Aug 15 22:15:43 EDT 2020
33
# DO NOT MODIFY
44

55

66
#
77
# miner "miner" v1.1
8-
# jcyr 2020.08.15.19:19:12
8+
# jcyr 2020.08.15.22:15:43
99
# SHA3-256 Miner Avalon Slave
1010
#
1111

@@ -184,18 +184,3 @@ set_interface_property reset SVD_ADDRESS_GROUP ""
184184

185185
add_interface_port reset rst reset Input 1
186186

187-
188-
#
189-
# connection point conduit
190-
#
191-
add_interface conduit conduit end
192-
set_interface_property conduit associatedClock clk
193-
set_interface_property conduit associatedReset reset
194-
set_interface_property conduit ENABLED true
195-
set_interface_property conduit EXPORT_OF ""
196-
set_interface_property conduit PORT_NAME_MAP ""
197-
set_interface_property conduit CMSIS_SVD_VARIABLES ""
198-
set_interface_property conduit SVD_ADDRESS_GROUP ""
199-
200-
add_interface_port conduit bsy bsy Output 1
201-

‎miner_ip/sha3_256_miner.v‎

Lines changed: 6 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -56,6 +56,7 @@ module sha3_256_miner (
5656

5757
parameter STAGES = 8; // Stages (2, 4, or 8)
5858

59+
localparam SHA3_STAGES = 24;
5960
localparam S = STAGES;
6061
localparam L2S = $clog2(S);
6162

@@ -78,7 +79,7 @@ wire ctl_run_w = ctl_r[1][0];
7879
// Only hashes out of phase 0 are valid except for the
7980
// 1st phase after run is enabled. Skip the 1st 8 cycles
8081
reg [4:0] valid_hash_r;
81-
wire valid_hash_w = valid_hash_r == 24;
82+
wire valid_hash_w = valid_hash_r == 0;
8283

8384
// Modulo 24 cycle counter
8485
reg [4:0] cycles_r;
@@ -145,7 +146,7 @@ round r_0(
145146
generate
146147
for(i = 1; i < S; i = i + 1)
147148
begin : L3
148-
wire [4:0] t0 = cycles_r - i[4:0] + ((cycles_r < i) ? 5'd24 : 5'b0);
149+
wire [4:0] t0 = cycles_r - i[4:0] + ((cycles_r < i) ? SHA3_STAGES : 5'b0);
149150
wire [4:0] t1 = {t0[4:L2S], i[L2S - 1:0]}; // Calc RC value offset for this stage
150151
round r_n(
151152
.clk(clk),
@@ -177,16 +178,16 @@ always @(posedge clk)
177178
begin
178179
if (rst | ~ctl_run_w) begin
179180
irq <= 0;
180-
valid_hash_r <= -1;
181+
valid_hash_r <= SHA3_STAGES;
181182
cycles_r <= -1;
182183
solution <= start_nonce;
183184
end
184185
else begin
185186
if (!irq) begin
186187
// Count up to 8 (end of 1st phase)
187-
valid_hash_r <= valid_hash_w ? valid_hash_r : valid_hash_r + 1'b1;
188+
valid_hash_r <= valid_hash_w ? 5'b0 : valid_hash_r - 1'b1;
188189
// Modulo 24 cycle count
189-
cycles_r <= cycles_r == 5'd23 ? 5'b0 : cycles_r + 1'b1;
190+
cycles_r <= cycles_r == (SHA3_STAGES - 1) ? 5'b0 : cycles_r + 1'b1;
190191

191192
if ((match_w | ctl_halt_w) & valid_hash_w) begin
192193
solution <= solution - S; // control[0]Solution is 8 cycles old.

‎overlay.dtso‎

Lines changed: 28 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,11 @@
55

66
fragment@0 {
77
target-path = "/soc/base-fpga-region";
8+
<<<<<<< HEAD
89
#address-cells = <0x1>;
10+
=======
11+
#address-cells = <0x1>;
12+
>>>>>>> small
913
#size-cells = <0x1>;
1014

1115
__overlay__ {
@@ -15,6 +19,7 @@
1519
fpga-bridges = <0xffffffff 0xffffffff>;
1620
ranges = <0x0 0x0 0xc0000000 0x20000000 0x1 0x0 0xff200000 0x200000>;
1721

22+
<<<<<<< HEAD
1823
clk_0 {
1924
compatible = "fixed-clock";
2025
#clock-cells = <0x0>;
@@ -134,10 +139,20 @@
134139
gpios = <0x2 0x7 0x0>;
135140
};
136141
};
142+
=======
143+
miner@100006000 {
144+
compatible = "cyr,miner-1.1", "dev,miner";
145+
reg = <0x00000001 0x00006000 0x00000080>;
146+
interrupt-parent = <0xffffffff>;
147+
interrupts = <0x0 0x28 0x4>;
148+
clocks = <0xffffffff>;
149+
};
150+
>>>>>>> small
137151
};
138152
};
139153

140154
__symbols__ {
155+
<<<<<<< HEAD
141156
clk_0 = "/fragment@0/__overlay__/clk_0";
142157
jtag_uart = "/fragment@0/__overlay__/serial@0x100002000";
143158
led_pio = "/fragment@0/__overlay__/gpio@0x100003000";
@@ -151,6 +166,13 @@
151166
fpga_bridge1 = "/fragment@0/__overlay__:fpga-bridges:4";
152167
intc = "/fragment@0/__overlay__/serial@0x100002000:interrupt-parent:0", "/fragment@0/__overlay__/gpio@0x100004000:interrupt-parent:0", "/fragment@0/__overlay__/gpio@0x100005000:interrupt-parent:0", "/fragment@0/__overlay__/miner@0x100006000:interrupt-parent:0";
153168
osc1 = "/fragment@0/__overlay__/gpio@0x100005000:clocks:0";
169+
=======
170+
miner_0 = "/fragment@0/__overlay__/miner@100006000";
171+
};
172+
173+
__fixups__ {
174+
intc = "/fragment@0/__overlay__/miner@100006000:interrupt-parent:0";
175+
>>>>>>> small
154176
};
155177

156178
__local_fixups__ {
@@ -159,6 +181,7 @@
159181

160182
__overlay__ {
161183

184+
<<<<<<< HEAD
162185
serial@0x100002000 {
163186
clocks = <0x0>;
164187
};
@@ -209,6 +232,11 @@
209232
gpios = <0x0>;
210233
};
211234
};
235+
=======
236+
miner@100006000 {
237+
clocks = <0x0>;
238+
};
239+
>>>>>>> small
212240
};
213241
};
214242
};

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