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@microdynamics-cpu

MicroDynamics CPU

Create free, easy-to-use RSIC-V processors and development environment.
README.md

Hi, TreeCore 👋

TreeCore contains a bundle of tools which aims to improve development experience of processor design. Now it mainly focus on processor frontend, ip, SoC architecture and system software field. We hope it can integrate multiple components to build a common workflow for agile hardware development from frontend to backend one day.

Help us to improve the project

You can issue bugs, pull requests, new features and modification suggestions freely. Your feedbacks could help us ensure a bright future for this project. We value and treasure every issue or contribution, big or small. 😄

Pinned

  1. tree-core-ide tree-core-ide Public

    🌳 The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation tool…

    JavaScript 96 14

  2. tree-core-cpu tree-core-cpu Public

    🌳 A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

    Scala 34 3

  3. tree-core-ip tree-core-ip Public

    A series of IP which has cycle-accurate, event-driven simulation models.

    SystemVerilog 3

  4. tree-core-asic tree-core-asic Public

    An Universal Simulation and Verification Environment for ASIC.

    Verilog 2

  5. tree-core-sim tree-core-sim Public

    A lightweight cloudFPGA prototype for processor simulation. It provides online scalable route resources with only open source synthesis toolset.

    C++ 2

  6. tree-core-backend tree-core-backend Public

    A core component of TreeCore IDE to execute heavy computing task in backstage.

    Rust 2

Repositories

Showing 10 of 23 repositories
  • tree-core-sim Public

    A lightweight cloudFPGA prototype for processor simulation. It provides online scalable route resources with only open source synthesis toolset.

    C++ 2 GPL-3.0 0 0 0 Updated Feb 9, 2024
  • tree-core-cpu Public

    🌳 A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, AM and difftest framework, etc) to design and verify.

    Scala 34 GPL-3.0 3 0 0 Updated Nov 8, 2023
  • tree-core-test Public

    A Software Test Sets for Processor Simulation and Verification

    C 1 GPL-3.0 0 0 0 Updated Jul 12, 2023
  • tree-core-ip Public

    A series of IP which has cycle-accurate, event-driven simulation models.

    SystemVerilog 3 GPL-3.0 0 0 0 Updated Jun 19, 2023
  • tree-core-runtime Public
    1 GPL-3.0 0 0 0 Updated Jun 13, 2023
  • tree-core-cicd Public

    A CI/CD environment for the processor simulation and verification.

    Python 1 GPL-3.0 0 0 0 Updated Jun 12, 2023
  • .github Public
    1 GPL-3.0 0 0 0 Updated May 18, 2023
  • tree-core-fpga Public

    An Universal FPGA Framework for SoC Simulation and Verification

    Verilog 2 GPL-3.0 0 0 0 Updated Mar 2, 2023
  • tree-core-bus Public

    A General Bus Generator which supporting AMBA, Wishbone, TileLink and ChipLink.

    C 1 GPL-3.0 0 0 0 Updated Jan 31, 2023
  • tree-core-rt Public
    C 1 GPL-3.0 0 0 0 Updated Jan 20, 2023
View all repositories

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