Traffic Light State Machine Using SR PORT and CIPs on PIC18F56Q24

The Signal Routing (SR) Port, is a peripheral that allows for flexible connections of other PIC® microcontroller peripherals without the need for dedicating Input/Output (I/O) pins and routing wires. The SR Port can be read and written from software just like a normal I/O port, and each pin in the port can optionally be configured to be clocked, allowing each pin to act as a flip-flop. The unique features of the SR Port make it possible to build state machines that can run without software intervention, which can greatly enhance the performance of the system. This project demonstrates how to implement a hardware-based state machine for controlling traffic lights using the SR PORT and other peripherals present on PIC18-Q24 microcontrollers.

Related Documentation

• MPLAB® Code Configurator
• PIC18-Q24 Family Product Page
• Signal Routing (SR) Ports
• Using the Signal Routing Port Module on 8-bit PIC® Microcontrollers

Software Used

• MPLAB® X IDE v6.20 or newer
• MPLAB® XC8 compiler v2.46 or newer
• MPLAB® Melody Library v2.8.0 or newer
• Microchip PIC18F-Q Series Device Support (DFP) v1.25.433 or newer

Hardware Used

• PIC18F56Q24
• PIC18F56Q24 Curiosity Nano Evaluation Kit
• Curiosity Nano Base for Click Boards™
• Mikroe Proto Click

State Machine Theory

Finite State Machines (FSMs) are an important concept in digital systems design. A traditional FSM consists of three main components:

1. Memory – The state machine memory holds the current system state.
2. Next State Logic – The Next State Logic dictates how the system will transition from one state to the next based on the current state and the input.
3. Output Logic – The output logic controls the outputs of the system based on the current state in the case of a Moore Machine, or a combination of inputs and the current state, in the case of a Mealy Machine.

When building embedded systems, FSMs are typically implemented in software. Using the SR PORT, Configurable Logic Cells (CLCs), and other peripherals present on PIC microcontrollers, it is possible to build functional state machines that can operate with little or no CPU intervention. Implementing state machines this way frees up the CPU to perfrom other tasks, which can greatly improve the system performance. The Figure below illustrates how state machines can be implemented using the SR PORT and CLCs:

Design

A traffic light controller needs to show a particular combination of lights to indicate whether North/South or East/West bound traffic can proceed. In this system, the output is a set of red, yellow, and green lights displaying whether traffic goes, slows down, or stops. The system also uses an emergency mode which will flash the red lights on and off until the emergency signal is cleared. A state machine can be designed to implement this functionality with no software intervention using SR PORT and Core Independent Peripherals (CIPs). For more details on how the logic was defined for this application, refer to ANxxxx.

To implement this state machine, a table showing all the possible states can be made. This particular system will be composed of five different states, each of which can be encoded using a three-bit number. The states are named based on their function: N/S for North/South bound traffic and E/W for East/West bound traffic. The three bits of the encoded number will be labled A₂,A₁, and A₀

State	Output	Encoding
N/S GO	N/S Green E/W Red	0b000
N/S SLOW	N/S Yellow E/W Red	0b001
E/W GO	E/W Green N/S Red	0b010
E/W SLOW	E/W Yellow N/S Red	0b011
Error	All lights flashing Red	0b100

Another table can be made to describe the outputs. In this system there are five outputs needed to control the traffic lights.

Name	Description
NSG	1 = N/S Green and E/W Red ON 0 = N/S Green and E/W Red OFF
NSY	1 = N/S Yellow and E/W Red ON 0 = N/S Yellow and E/W Red OFF
EWG	1 = E/W Green and N/S Red ON 0 = E/W Green and N/S Red OFF
EWY	1 = E/W Yellow and N/S Red ON 0 = E/W Yellow and N/S Red OFF
ERR	1 = All red lights flash ON/OFF 0 = No error state

A state transistion diagram can be made to show the transitions between the states. The input to the system is the error signal which will be labeled E.

Once the state transition diagram has been drawn, a state transistion table can be made of the input and state encoding values. This will be used to derive boolean equations that can be implemented using the on-chip CLCs.

Using the state transition table, the following equations were derived:

To simplify the implementation of these equations using the on-chip CLCs, the equations are re-arranged from their Sum-of-Products (SOP) form to their equivalent Product-of-Sums (POS) form:

Once the next state logic has been determined, another table can be made to define the output based on the state:

This table can be used to derive equations for the output logic.

Since the error state is the only state where A₂ is 1, A₂ can be used directly as the ERR output:

The timing of the traffic lights is controlled by the state machine clock. To vary the timing so that the duration of the Slow states are shorter than the duration of the Go states, one of the dual output Pulse-Width-Modulator (PWM) modules were used as the state machine clock source. The PWM is configured to have a frequency of 0.1 Hz with a second pulse generated three seconds after the first pulse. These two signals can be labeled as P₁ for the first pulse, and P₂ for the second. A CLC is used to OR these two pulses together and is used as the clock source for the SR Port peripheral. This same CLC is also used to gate one of the pulses when the system is in the error state so the timing will be correctly synced when the error state is exited. The logic expression for the system clock can be implemented like so:

Implementation

Once all the logic has been defined, the system can be implemented using the SR PORT and CLCs. Three bits of the SR PORT will be used as the memory elements for the state machine and each boolean logic equation can be implemented using one CLC each. The specific CLCs were chosen to accommodate the hardware connections of the Curiosity Nano and Curiosity Nano Base boards. A small circuit was prototyped using the Mikroe Proto Click board to simulate traffic lights. The circuit takes the five inputs that have been defined and lights an array of LEDs appropriately:
Schematic


Traffic Light Demo

The table below shows the mapping between logic outputs and CLCs:

CLC Instance	Logic Output
CLC1	NSG
CLC2	NSY
CLC3	A0
CLC4	A1
CLC5	EWG
CLC6	EWY
CLC7	A2
CLC8	CLK

The table below shows the output pin mapping:

Signal	Pin	Type
NSG	RA3	Output
NSY	RF5	Output
EWG	RA4	Output
EWY	RA0	Output
ERR	RB0	Input

To configure the on-chip CLCs, MPLAB Melody was used. Melody is a graphical tool that allows for simple and easy configuration of any of the on-chip peripherals present on PIC microcontrollers. The following images show the Melody configurations for each of the CLCs:

CLC1

CLC2

CLC3

CLC4

CLC5

CLC6

CLC7

CLC8

The SR PORT was also configured using MPLAB Melody

SR PORT

Summary

The SR PORT allows for advanced interconnectivity between CIPs on PIC microcontrollers. It can individually configure each bit as a flip-flop, allowing the SR PORT to act as the memory element in a hardware state machine. Using the SR PORT in combination with the CLCs makes it possible to build core-independent state machines that can offload tasks from the CPU and greatly increase system performance.