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namco_c139: semi working implementation (ASIO, async, threaded) #13867

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cee98b9
namco_c139: semi working implementation (ASIO, async, threaded)
SailorSat Jun 22, 2025
78d023c
c139: minor improvements
SailorSat Jun 29, 2025
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942 changes: 913 additions & 29 deletions src/mame/namco/namco_c139.cpp
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53 changes: 43 additions & 10 deletions src/mame/namco/namco_c139.h
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Original file line number Diff line number Diff line change
Expand Up @@ -23,43 +23,76 @@

// ======================> namco_c139_device

class namco_c139_device : public device_t,
public device_memory_interface
class namco_c139_device : public device_t
{
public:
// construction/destruction
namco_c139_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);

auto irq_cb() { return m_irq_cb.bind(); }

// I/O operations
void data_map(address_map &map) ATTR_COLD;
void regs_map(address_map &map) ATTR_COLD;

uint16_t status_r();

uint16_t ram_r(offs_t offset);
void ram_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);

void data_map(address_map &map) ATTR_COLD;
uint16_t reg_r(offs_t offset);
void reg_w(offs_t offset, uint16_t data, uint16_t mem_mask = ~0);

void sci_de_hack(uint8_t data);


protected:
// device-level overrides
// virtual void device_validity_check(validity_checker &valid) const;
virtual void device_start() override ATTR_COLD;
virtual void device_stop() override ATTR_COLD;
virtual void device_reset() override ATTR_COLD;
virtual space_config_vector memory_space_config() const override;

devcb_write_line m_irq_cb;

private:
const address_space_config m_space_config;
uint16_t* m_ram = nullptr;
uint16_t m_ram[0x2000];
uint16_t m_reg[0x0010];

std::string m_localhost;
std::string m_localport;
std::string m_remotehost;
std::string m_remoteport;

emu_timer *m_tick_timer;

class context;
std::unique_ptr<context> m_context;

uint8_t m_buffer[0x200];

uint16_t m_linktimer;
uint8_t m_linkid;
uint8_t m_txsize;
uint8_t m_txblock;
uint8_t m_reg_f3;

TIMER_CALLBACK_MEMBER(tick_timer_callback);

void comm_tick();
void read_data(unsigned data_size);
unsigned read_frame(unsigned data_size);
unsigned find_sync_bit(unsigned tx_offset, unsigned tx_mask);
void send_data(unsigned data_size);
void send_frame(unsigned data_size);
};


// device type definition
DECLARE_DEVICE_TYPE(NAMCO_C139, namco_c139_device)



//**************************************************************************
// GLOBAL VARIABLES
//**************************************************************************



#endif // MAME_NAMCO_NAMCO_C139_H
11 changes: 9 additions & 2 deletions src/mame/namco/namcos2.cpp
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Expand Up @@ -691,7 +691,7 @@ void namcos2_state::namcos2_68k_default_cpu_board_am(address_map &map)
map(0x420000, 0x42003f).rw(m_c123tmap, FUNC(namco_c123tmap_device::control16_r), FUNC(namco_c123tmap_device::control16_w));
map(0x440000, 0x44ffff).r(FUNC(namcos2_state::c116_r)).w(m_c116, FUNC(namco_c116_device::write)).umask16(0x00ff).cswidth(16);
map(0x460000, 0x460fff).mirror(0x00f000).rw(FUNC(namcos2_state::dpram_word_r), FUNC(namcos2_state::dpram_word_w));
map(0x480000, 0x483fff).rw(m_sci, FUNC(namco_c139_device::ram_r), FUNC(namco_c139_device::ram_w));
map(0x480000, 0x483fff).m(m_sci, FUNC(namco_c139_device::data_map));
map(0x4a0000, 0x4a000f).m(m_sci, FUNC(namco_c139_device::regs_map));
}

Expand Down Expand Up @@ -1707,7 +1707,8 @@ void namcos2_state::configure_common_standard(machine_config &config)

NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_1);

NAMCO_C139(config, m_sci, 0);
NAMCO_C139(config, m_sci, 0U);
m_sci->irq_cb().set(FUNC(namcos2_state::sci_int_w));

SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
m_screen->set_raw(MAIN_OSC_CLOCK/8, 384, 0*8, 36*8, 264, 0*8, 28*8);
Expand Down Expand Up @@ -1750,6 +1751,12 @@ TIMER_DEVICE_CALLBACK_MEMBER(namcos2_state::screen_scanline)
}
}

void namcos2_state::sci_int_w(int state)
{
m_master_intc->sci_irq_trigger();
m_slave_intc->sci_irq_trigger();
}

void namcos2_state::configure_c123tmap_standard(machine_config &config)
{
NAMCO_C123TMAP(config, m_c123tmap);
Expand Down
1 change: 1 addition & 0 deletions src/mame/namco/namcos2.h
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Expand Up @@ -226,6 +226,7 @@ enum

int get_pos_irq_scanline() { return (m_c116->get_reg(5) - 32) & 0xff; }
TIMER_DEVICE_CALLBACK_MEMBER(screen_scanline);
void sci_int_w(int state);

required_shared_ptr<u8> m_dpram; /* 2Kx8 */
optional_shared_ptr<u16> m_spriteram;
Expand Down
16 changes: 13 additions & 3 deletions src/mame/namco/namcos21.cpp
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Expand Up @@ -385,6 +385,7 @@ class namcos21_state : public driver_device
std::unique_ptr<uint8_t[]> m_eeprom;

TIMER_DEVICE_CALLBACK_MEMBER(screen_scanline);
void sci_int_w(int state);

uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);

Expand Down Expand Up @@ -562,7 +563,7 @@ void namcos21_state::winrun_master_map(address_map &map)
map(0x800000, 0x87ffff).rom().region("data", 0);
map(0x900000, 0x90ffff).ram().share("sharedram");
map(0xa00000, 0xa00fff).rw(FUNC(namcos21_state::dpram_word_r), FUNC(namcos21_state::dpram_word_w));
map(0xb00000, 0xb03fff).rw(m_sci, FUNC(namco_c139_device::ram_r), FUNC(namco_c139_device::ram_w));
map(0xb00000, 0xb03fff).m(m_sci, FUNC(namco_c139_device::data_map));
map(0xb80000, 0xb8000f).m(m_sci, FUNC(namco_c139_device::regs_map));
}

Expand All @@ -575,7 +576,7 @@ void namcos21_state::winrun_slave_map(address_map &map)
map(0x800000, 0x87ffff).rom().region("data", 0);
map(0x900000, 0x90ffff).ram().share("sharedram");
map(0xa00000, 0xa00fff).rw(FUNC(namcos21_state::dpram_word_r), FUNC(namcos21_state::dpram_word_w));
map(0xb00000, 0xb03fff).rw(m_sci, FUNC(namco_c139_device::ram_r), FUNC(namco_c139_device::ram_w));
map(0xb00000, 0xb03fff).m(m_sci, FUNC(namco_c139_device::data_map));
map(0xb80000, 0xb8000f).m(m_sci, FUNC(namco_c139_device::regs_map));
}

Expand Down Expand Up @@ -869,6 +870,13 @@ TIMER_DEVICE_CALLBACK_MEMBER(namcos21_state::screen_scanline)
m_gpu_intc->pos_irq_trigger();
}

void namcos21_state::sci_int_w(int state)
{
m_master_intc->sci_irq_trigger();
m_slave_intc->sci_irq_trigger();
m_gpu_intc->sci_irq_trigger();
}

void namcos21_state::configure_c148_standard(machine_config &config)
{
NAMCO_C148(config, m_master_intc, 0, m_maincpu, true);
Expand Down Expand Up @@ -903,7 +911,9 @@ void namcos21_state::winrun(machine_config &config)

configure_c148_standard(config);
NAMCO_C148(config, m_gpu_intc, 0, "gpu", false);
NAMCO_C139(config, m_sci, 0);

NAMCO_C139(config, m_sci, 0U);
m_sci->irq_cb().set(FUNC(namcos21_state::sci_int_w));

config.set_maximum_quantum(attotime::from_hz(6000)); /* 100 CPU slices per frame */

Expand Down
13 changes: 11 additions & 2 deletions src/mame/namco/namcos21_c67.cpp
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Expand Up @@ -353,6 +353,7 @@ class namcos21_c67_state : public driver_device

TIMER_DEVICE_CALLBACK_MEMBER(screen_scanline);

void sci_int_w(int state);
void yield_hack(int state);

uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
Expand Down Expand Up @@ -456,7 +457,7 @@ void namcos21_c67_state::common_map(address_map &map)
map(0x800000, 0x8fffff).rom().region("data", 0);
map(0x900000, 0x90ffff).ram().share("sharedram");
map(0xa00000, 0xa00fff).rw(FUNC(namcos21_c67_state::dpram_word_r), FUNC(namcos21_c67_state::dpram_word_w));
map(0xb00000, 0xb03fff).rw(m_sci, FUNC(namco_c139_device::ram_r), FUNC(namco_c139_device::ram_w));
map(0xb00000, 0xb03fff).m(m_sci, FUNC(namco_c139_device::data_map));
map(0xb80000, 0xb8000f).m(m_sci, FUNC(namco_c139_device::regs_map));
map(0xc00000, 0xcfffff).rom().mirror(0x100000).region("edata", 0);
}
Expand Down Expand Up @@ -781,6 +782,12 @@ TIMER_DEVICE_CALLBACK_MEMBER(namcos21_c67_state::screen_scanline)
}
}

void namcos21_c67_state::sci_int_w(int state)
{
m_master_intc->sci_irq_trigger();
m_slave_intc->sci_irq_trigger();
}

void namcos21_c67_state::configure_c148_standard(machine_config &config)
{
NAMCO_C148(config, m_master_intc, 0, m_maincpu, true);
Expand Down Expand Up @@ -827,7 +834,9 @@ void namcos21_c67_state::namcos21(machine_config &config)
m_namcos21_3d->set_framebuffer_size(496,480);

configure_c148_standard(config);
NAMCO_C139(config, m_sci, 0);

NAMCO_C139(config, m_sci, 0U);
m_sci->irq_cb().set(FUNC(namcos21_c67_state::sci_int_w));

PALETTE(config, m_palette).set_format(palette_device::xBRG_888, 0x10000/2);

Expand Down
41 changes: 26 additions & 15 deletions src/mame/namco/namcos21_de.cpp
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Expand Up @@ -14,17 +14,6 @@ Driver's Eyes works,
(probably wants angle sent by main board?)

-On demo screen, should fog effects be turned off?

NOTES:

Driver's Eyes
not yet working

TODO:

Driver's Eyes
add communications for Left and Right screen (linked C139 or something else?)

*/

#include "emu.h"
Expand Down Expand Up @@ -61,6 +50,7 @@ class namco_de_pcbstack_device : public device_t
namco_de_pcbstack_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);

void configure_c148_standard(machine_config &config);
void sci_de_hack(uint8_t data);

protected:
virtual void device_add_mconfig(machine_config &config) override ATTR_COLD;
Expand Down Expand Up @@ -111,6 +101,7 @@ class namco_de_pcbstack_device : public device_t
std::unique_ptr<uint8_t[]> m_eeprom;

TIMER_DEVICE_CALLBACK_MEMBER(screen_scanline);
void sci_int_w(int state);

uint32_t screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);

Expand Down Expand Up @@ -176,7 +167,8 @@ void namco_de_pcbstack_device::device_add_mconfig(machine_config &config)
NVRAM(config, "nvram", nvram_device::DEFAULT_ALL_1);

configure_c148_standard(config);
NAMCO_C139(config, m_sci, 0);
NAMCO_C139(config, m_sci, 0U);
m_sci->irq_cb().set(FUNC(namco_de_pcbstack_device::sci_int_w));

SCREEN(config, m_screen, SCREEN_TYPE_RASTER);
// TODO: basic parameters to get 60.606060 Hz, x2 is for interlace
Expand Down Expand Up @@ -353,7 +345,7 @@ void namco_de_pcbstack_device::driveyes_common_map(address_map &map)
map(0x800000, 0x8fffff).rom().region("data", 0);
map(0x900000, 0x90ffff).ram().share("sharedram");
map(0xa00000, 0xa00fff).rw(FUNC(namco_de_pcbstack_device::dpram_word_r), FUNC(namco_de_pcbstack_device::dpram_word_w));
map(0xb00000, 0xb03fff).rw(m_sci, FUNC(namco_c139_device::ram_r), FUNC(namco_c139_device::ram_w));
map(0xb00000, 0xb03fff).m(m_sci, FUNC(namco_c139_device::data_map));
map(0xb80000, 0xb8000f).m(m_sci, FUNC(namco_c139_device::regs_map));
}

Expand Down Expand Up @@ -440,6 +432,17 @@ TIMER_DEVICE_CALLBACK_MEMBER(namco_de_pcbstack_device::screen_scanline)
}
}

void namco_de_pcbstack_device::sci_int_w(int state)
{
m_master_intc->sci_irq_trigger();
m_slave_intc->sci_irq_trigger();
}

void namco_de_pcbstack_device::sci_de_hack(uint8_t data)
{
m_sci->sci_de_hack(data);
}

void namco_de_pcbstack_device::configure_c148_standard(machine_config &config)
{
NAMCO_C148(config, m_master_intc, 0, m_maincpu, true);
Expand Down Expand Up @@ -485,6 +488,7 @@ class namcos21_de_state : public driver_device
{ }

void driveyes(machine_config &config);
void init_driveyes();

private:
required_device_array<namco_de_pcbstack_device, 3> m_pcb;
Expand Down Expand Up @@ -828,8 +832,15 @@ ROM_START( driveyes )
ROM_END


void namcos21_de_state::init_driveyes()
{
m_pcb[0]->sci_de_hack(0);
m_pcb[1]->sci_de_hack(1);
m_pcb[2]->sci_de_hack(2);
}


/* YEAR NAME PARENT MACHINE INPUT CLASS INIT MONITOR COMPANY FULLNAME FLAGS */

// 3 PCB stacks in a single cage (3x 4 PCBs) linked for 3 screen panorama, boards look similar to original Namco System 21 (not 21B) including TMS320C25 DSP, but use C68 I/O MCU and sprite chip instead of "68000 'GPU'" ?
GAME( 1992, driveyes, 0, driveyes, driveyes, namcos21_de_state, empty_init, ROT0, "Namco", "Driver's Eyes (Japan) (1992/01/10, Main Ver 2.1, Sub Ver 1.1)", MACHINE_NOT_WORKING | MACHINE_IMPERFECT_GRAPHICS | MACHINE_NODEVICE_LAN)

GAME( 1992, driveyes, 0, driveyes, driveyes, namcos21_de_state, init_driveyes, ROT0, "Namco", "Driver's Eyes (Japan) (1992/01/10, Main Ver 2.1, Sub Ver 1.1)", MACHINE_IMPERFECT_GRAPHICS)
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