add a reference to sv-tests #60
Conversation
Not all tools support all syntax constructs, before using a new feature, checking that it is widely supported helps with interoperability. For instance, SystemVerilog interfaces, as discussed in #52, are not available yet to Yosys and icarus verilog.
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Thanks for the contribution @josuah sv-tests is indeed a useful tool, though it does only cover open source tools. We want blocks written using the lowRISC style guide to be broadly useable across the whole EDA ecosystem which includes many proprietary tools. Often limitations in language usage are born out from past experience with proprietary tools. So it's not as simple as looking at a feature matrix and seeing FooSynth doesn't support interfaces (if you can even find such a feature matrix). Unfortunately due to licensing and confidentiality agreements publicly documenting specific issues with specific tools is also fraught with difficulty. So sv-tests alone isn't sufficient for our purposes, nor could we put together a similar matrix for proprietary tools (or at least make a public one). Though the point is taken we should provide further justification for the exclusion of interfaces. Some wording to explain that interfaces have been observed to be poorly supported in some EDA flows could suffice. |
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I just noticed this remained open and I did not answer. |
This is a request for comments.
In #52 were discussed the use of SystemVerilog interfaces, and the reason stated was the absence of a complete tooling support. It is true that a few major tools part of the open source toolchain do not support them fully, like yosys for which it is WIP.
What about a referencne to sv-tests? This would hint that the motivation is not that interfaces are a confusing feature, but rather a poorly supported one.
If not interesting to have it there, feel free to close this.