[DRAFT] Bring up of Darjeeling simulations using Verilator #27105
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Expressed as a single bit vector PartInvDefault was of illegal width for Darjeeling. Section 6.9.1 of the SystemVerilog specification permits implementations to be constrained to 65536-bit wide vectors. The much larger OTP of Darjeeling was thus unacceptable to Verilator. Annotate the partition and item names in the auto-generated SV package. Co-authored-by: Rupert Swarbrick <[email protected]> Signed-off-by: Adrian Lees <[email protected]>
Set up OTP image building within Bazel environment based upon a modified form of that used with Earl Grey. Enlarge partition in OTP to accommodate the 102 alerts of Darjeeling. Signed-off-by: Adrian Lees <[email protected]>
Add Darjeeling verilator environment consisting of Verilator- specific chip implementation that wraps the `top_darjeeling` module. Test bench environment is based on that of Earl Grey with modifications to accommodate the different set of memories present in Darjeeling. Signed-off-by: Adrian Lees <[email protected]>
DO NOT merge this commit. Temporary changes made for Darjeeling bring up within Verilator simulation, but these break operation with Earl Grey. Signed-off-by: Adrian Lees <[email protected]>
alees24
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Verilator support was added now in master. Closing this older PR. Thanks for looking into it Adrian. |
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The changes in this PR are enough to permit Verilator simulations of Darjeeling to be built and executed with a few caveats and manual steps to be resolved; hence it is a draft PR at present:
The build process with Bazel is still emitting an OTP image for Earl Grey and not Darjeeling, despite having specified '--//hw/top=darjeeling' on the command line.PartInvDefaultwithin otp_ctrl_part_pkg needs still to be resolved (see PRs [otp_ctrl] Expand overly wide literals (vectors) #26998 and [otp_ctrl] Re-express PartInvDefault as an array #27069)With those caveats, this PR may be used to build and run a Darjeeling+Verilator simulation environment using:
uart_smoketest runs to completion without waveform capture in about 100s on a modest laptop (excluding chip compilation time, obviously).
So this is presently a proof-of-concept to sound out what was required, and is raised as a draft PR for visibility and to share the work done before the above issues are properly resolved.