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192 Open 660 Closed
192 Open 660 Closed
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Issues list

[rtl] Implement mcounteren CSR Component:RTL RTL issue Type:Enhancement Feature requests, enhancements
#1974 opened Jan 19, 2023 by GregAC
[rtl] Implement cycle/instret/time/hmpcountern CSRs Component:RTL RTL issue Priority:P3 Type:Bug Bugs
#1973 opened Jan 19, 2023 by GregAC
3
Ibex simple system Type:Question Questions
#1972 opened Jan 18, 2023 by sadjadtu
2
[rtl, doc] Consider hardening data_rvalid_i for 2-stage config Component:Doc Documentation issue Component:RTL RTL issue Type:Enhancement Feature requests, enhancements
#1970 opened Jan 16, 2023 by vogelpi
[Confirmation] Regression and Coverage data metrics Type:Question Questions
#1966 opened Dec 23, 2022 by Shaileshkavar
1
memory initialization Type:Question Questions
#1965 opened Dec 22, 2022 by sadjadtu
2
[dv] Formally verify PMP functionality Component:DV Design verification (DV) or testing issue Priority:P3 Type:Enhancement Feature requests, enhancements
#1963 opened Dec 8, 2022 by GregAC V3
1
Ask a question related to Ibex Type:Question Questions
#1961 opened Dec 6, 2022 by NikosDelijohn
3
mismatch between spike sim and rtl sim Type:Question Questions
#1959 opened Dec 1, 2022 by hyperion009
2
.S file is not generated for riscv_arithmetic_basic_test Type:Question Questions
#1956 opened Nov 25, 2022 by Shaileshkavar
2
Error when I make in ibex UVM DV Component:DV Design verification (DV) or testing issue Type:Bug Bugs Type:Question Questions
#1955 opened Nov 22, 2022 by Zhengshuhang
3
Error Elaborating IF State with Cadence Tools Type:Bug Bugs
#1953 opened Nov 18, 2022 by aroelke
1
[cosim] Sort out error/pmp failure behaviour on unaligned accesses Component:DV Design verification (DV) or testing issue Priority:P3
#1948 opened Nov 17, 2022 by GregAC V3
1
[dv] PMP Coverage Holes Component:DV Design verification (DV) or testing issue Priority:P2
#1944 opened Nov 16, 2022 by GregAC V3
5
bitmanip s Type:Question Questions
#1941 opened Nov 16, 2022 by hyperion009
Missing a module tc_clk_gating Type:Question Questions
#1940 opened Nov 16, 2022 by hyperion009
1
[dv] Build a regression system for directed simple system co-sim tests Component:DV Design verification (DV) or testing issue Component:Test A test or set of tests Type:Enhancement Feature requests, enhancements
#1936 opened Nov 15, 2022 by GregAC V3
[dv] Psuedo instruction coverage for Bitmanip
#1926 opened Nov 13, 2022 by GregAC V3
[dv] Small architectural coverage issues to investigate Component:DV Design verification (DV) or testing issue Priority:P3 Type:Task Tasks, to-do list.
#1925 opened Nov 13, 2022 by GregAC
5 tasks
V3
1
[dv] Add force pass and terminate functionality to UVM base test
#1892 opened Nov 2, 2022 by GregAC V3
@GregAC
1
Problem on Building Simulation with RV32E Type:Question Questions
#1860 opened Oct 18, 2022 by sadjadtu
7
Record when a testcase fails by the double_fault detector, add indicator to summary logfile Type:Enhancement Feature requests, enhancements
#1857 opened Oct 14, 2022 by hcallahan-lowrisc V3
Consider adding explicit enable for qualifying DBG_CAUSE Component:RTL RTL issue Type:Enhancement Feature requests, enhancements
#1856 opened Oct 14, 2022 by hcallahan-lowrisc D3
[dv] Randomize hart_id Component:DV Design verification (DV) or testing issue Type:Enhancement Feature requests, enhancements
#1852 opened Oct 14, 2022 by GregAC V3
[dv] Prettify invalid option to column Type:Bug Bugs
#1843 opened Oct 7, 2022 by marnovandermaas
1
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