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[wb_acq_core] Channels with 768 bits width causes alignment issues #18

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augustofg opened this issue Apr 12, 2023 · 0 comments
Open

[wb_acq_core] Channels with 768 bits width causes alignment issues #18

augustofg opened this issue Apr 12, 2023 · 0 comments

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@augustofg
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When testing an acquisition with 768 bits (24 atoms of 32 bits each) sample width, the samples are not properly aligned during read, so we get a slice of the previous sample mixed with the actual sample. Doing some investigation we determined that the TRIG_POS register is calculated incorrectly.
guilhermerc added a commit to lnls-dig/fofb-ctrl-gw that referenced this issue Apr 13, 2023
@guilhermerc
afc_ref_fofb_ctrl_gen.vhd: acq tweaks/workarounds
55cf922 
1. Changed FOFB sys id channel width from 768 to 1024 as a workaround
   for the bug described on [1];
2. Swapped each 2 16-bit FOFB processing setpoints so they end up being
   allocated on RAM in descending order after ACQ endiannes procedures.
3. Reverse the blocks of signals.

[1] lnls-dig/infra-cores#18
guilhermerc added a commit to lnls-dig/fofb-ctrl-gw that referenced this issue Apr 13, 2023
@guilhermerc
afc_ref_fofb_ctrl_gen.vhd: acq tweaks/workarounds
4d4c97e 
1. Changed FOFB sys id channel width from 768 to 1024 as a workaround
   for the bug described on [1];
2. Swapped each 2 16-bit FOFB processing setpoints so they end up being
   allocated on RAM in descending order after ACQ endianness procedures.
3. Repositioned the acquired signals to keep consistency with other ACQ
   cores.

[1] lnls-dig/infra-cores#18
guilhermerc added a commit to lnls-dig/fofb-ctrl-gw that referenced this issue Apr 13, 2023
@guilhermerc
afc_ref_fofb_ctrl_gen.vhd: acq tweaks/workarounds
1e07979 
1. Changed FOFB sys id channel width from 768 to 1024 as a workaround
   for the bug described on [1];
2. Swapped each 2 16-bit FOFB processing setpoints so they end up being
   allocated on RAM in descending order after ACQ endianness procedures.
3. Repositioned the acquired signals to keep consistency with other ACQ
   cores.

[1] lnls-dig/infra-cores#18
guilhermerc added a commit to lnls-dig/fofb-ctrl-gw that referenced this issue Apr 17, 2023
@guilhermerc
afc_ref_fofb_ctrl_gen.vhd: acq tweaks/workarounds
aa19275 
1. Changed FOFB sys id channel width from 768 to 1024 as a workaround
   for the bug described on [1];
2. Swapped each 2 16-bit FOFB processing setpoints so they end up being
   allocated on RAM in descending order after ACQ endianness procedures.
3. Repositioned the acquired signals to keep consistency with other ACQ
   cores.

[1] lnls-dig/infra-cores#18
guilhermerc added a commit to lnls-dig/fofb-ctrl-gw that referenced this issue Apr 17, 2023
@guilhermerc
afc_ref_fofb_ctrl_gen.vhd: acq tweaks/workarounds
9fc9270 
1. Changed FOFB sys id channel width from 768 to 1024 as a workaround
   for the bug described on [1];
2. Swapped each 2 16-bit FOFB processing setpoints so they end up being
   allocated on RAM in descending order after ACQ endianness procedures.
3. Repositioned the acquired signals to keep consistency with other ACQ
   cores.

[1] lnls-dig/infra-cores#18
guilhermerc added a commit to lnls-dig/fofb-ctrl-gw that referenced this issue Apr 18, 2023
@guilhermerc
afc_ref_fofb_ctrl_gen.vhd: acq tweaks/workarounds
f12460f 
1. Changed FOFB sys id channel width from 768 to 1024 as a workaround
   for the bug described on [1];
2. Swapped each 2 16-bit FOFB processing setpoints so they end up being
   allocated on RAM in descending order after ACQ endianness procedures.
3. Repositioned the acquired signals to keep consistency with other ACQ
   cores.

[1] lnls-dig/infra-cores#18
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