wb_orbit_intlk testbench refactoring #106
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This is in anticipation to creating a new testbench compatible with NVC and GHDL.
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guilhermerc
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Sep 25, 2024
To avoid depending on proprietary (and expensive) mixed-language HDL simulators, migrate the orbit interlock testbench to VHDL, add support for NVC and GHDL. All tests: Clear interlock latches before testing the interlock condition. Test 7: The orbit_intlk_trans_min_x/y thresholds were set to 0, but the decimated position was negative, causing an interlock condition.
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