Exposes the minimum sum threshold detection via Wishbone

lnls-dig · Sep 26, 2024 · a36f665 · a36f665
1 parent 41f63c5
commit a36f665
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Showing 11 changed files with 178 additions and 84 deletions.
diff --git a/hdl/modules/wb_orbit_intlk/orbit_intlk.vhd b/hdl/modules/wb_orbit_intlk/orbit_intlk.vhd
@@ -181,6 +181,10 @@ port
   -- conditional to intlk_en_i
   intlk_ang_o                                : out std_logic;
 
+  -- '1' if decim_us/ds_pos_sum_i >  intlk_min_sum_i, '0' otherwise.
+  -- Clock domain: ref_clk_i
+  intlk_sum_bigger_any_o                     : out std_logic;
+
   -- only cleared when intlk_clr_i is asserted
   intlk_ltc_o                                : out std_logic;
   -- conditional to intlk_en_i
@@ -423,6 +427,7 @@ begin
     end if;
   end process;
 
+  intlk_sum_bigger_any_o <= intlk_sum_bigger_any;
   intlk_sum_bigger_en <= '1' when intlk_min_sum_en_i = '0' else intlk_sum_bigger_any;
 
   -----------------------------

diff --git a/hdl/modules/wb_orbit_intlk/orbit_intlk_pkg.vhd b/hdl/modules/wb_orbit_intlk/orbit_intlk_pkg.vhd
@@ -191,6 +191,10 @@ package orbit_intlk_pkg is
     -- conditional to intlk_en_i
     intlk_ang_o                                : out std_logic;
 
+    -- '1' if decim_us/ds_pos_sum_i >  intlk_min_sum_i, '0' otherwise.
+    -- Clock domain: ref_clk_i
+    intlk_sum_bigger_any_o                     : out std_logic;
+
     -- only cleared when intlk_clr_i is asserted
     intlk_ltc_o                                : out std_logic;
     -- conditional to intlk_en_i

diff --git a/hdl/modules/wb_orbit_intlk/wb_orbit_intlk.vhd b/hdl/modules/wb_orbit_intlk/wb_orbit_intlk.vhd
@@ -520,6 +520,8 @@ begin
     intlk_ang_smaller_ltc_o                    => intlk_ang_smaller_ltc,
     intlk_ang_smaller_o                        => intlk_ang_smaller,
 
+    intlk_sum_bigger_any_o                     => regs_in.sts_min_sum_bigger_i,
+
     intlk_ltc_o                                => intlk_ltc,
     intlk_o                                    => intlk
   );

diff --git a/hdl/modules/wb_orbit_intlk/wbgen/doc/orbit_intlk_regs_wb.html b/hdl/modules/wb_orbit_intlk/wbgen/doc/orbit_intlk_regs_wb.html
@@ -1035,10 +1035,27 @@ <h3><a name="sect_2_0">2. HDL symbol</a></h3>
 
 </td>
 <td  class="td_pblock_right">
-orbit_intlk_sts_reserved_i[1:0]
+orbit_intlk_sts_min_sum_bigger_i
 </td>
 <td  class="td_arrow_right">
-&lArr;
+&larr;
+</td>
+</tr>
+<tr>
+<td  class="td_arrow_left">
+
+</td>
+<td  class="td_pblock_left">
+
+</td>
+<td  class="td_sym_center">
+
+</td>
+<td  class="td_pblock_right">
+orbit_intlk_sts_reserved_i
+</td>
+<td  class="td_arrow_right">
+&larr;
 </td>
 </tr>
 <tr>
@@ -2063,8 +2080,11 @@ <h3><a name="sect_3_2">3.2. General Status Signals</a></h3>
 </td>
 </tr>
 <tr>
-<td style="border: solid 1px black;" colspan=2  class="td_field">
-RESERVED[1:0]
+<td style="border: solid 1px black;" colspan=1  class="td_field">
+RESERVED
+</td>
+<td style="border: solid 1px black;" colspan=1  class="td_field">
+MIN_SUM_BIGGER
 </td>
 <td style="border: solid 1px black;" colspan=1  class="td_field">
 ANG_SMALLER_LTC
@@ -2083,9 +2103,6 @@ <h3><a name="sect_3_2">3.2. General Status Signals</a></h3>
 </td>
 <td style="border: solid 1px black;" colspan=1  class="td_field">
 ANG_SMALLER_Y
-</td>
-<td >
-
 </td>
 </tr>
 </table>
@@ -2373,6 +2390,10 @@ <h3><a name="sect_3_2">3.2. General Status Signals</a></h3>
 </b>[<i>read-only</i>]: Angular Smaller Latched
 <br>Angular Smaller Latched
 <li><b>
+MIN_SUM_BIGGER
+</b>[<i>read-only</i>]: Minimum sum threshold detection
+<br>'1' if the BPM amplitudes sums are bigger than the value specified in min_sum, '0' otherwise.
+<li><b>
 RESERVED
 </b>[<i>read-only</i>]: Reserved
 <br>Ignore on write, read as 0's

diff --git a/hdl/modules/wb_orbit_intlk/wbgen/orbit_intlk_regs.h b/hdl/modules/wb_orbit_intlk/wbgen/orbit_intlk_regs.h
@@ -3,7 +3,7 @@
 
   * File           : orbit_intlk_regs.h
   * Author         : auto-generated by wbgen2 from wb_orbit_intlk_regs.wb
-  * Created        : Mon Oct 25 13:33:06 2021
+  * Created        : Tue Sep 24 11:12:27 2024
   * Standard       : ANSI C
 
     THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_orbit_intlk_regs.wb
@@ -156,11 +156,11 @@
 /* definitions for field: Angular Smaller Latched in reg: General Status Signals */
 #define ORBIT_INTLK_STS_ANG_SMALLER_LTC       WBGEN2_GEN_MASK(29, 1)
 
+/* definitions for field: Minimum sum threshold detection in reg: General Status Signals */
+#define ORBIT_INTLK_STS_MIN_SUM_BIGGER        WBGEN2_GEN_MASK(30, 1)
+
 /* definitions for field: Reserved in reg: General Status Signals */
-#define ORBIT_INTLK_STS_RESERVED_MASK         WBGEN2_GEN_MASK(30, 2)
-#define ORBIT_INTLK_STS_RESERVED_SHIFT        30
-#define ORBIT_INTLK_STS_RESERVED_W(value)     WBGEN2_GEN_WRITE(value, 30, 2)
-#define ORBIT_INTLK_STS_RESERVED_R(reg)       WBGEN2_GEN_READ(reg, 30, 2)
+#define ORBIT_INTLK_STS_RESERVED              WBGEN2_GEN_MASK(31, 1)
 
 /* definitions for register: Minimum sum threshold */
 

diff --git a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.vhd b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : wb_orbit_intlk_regs.vhd
 -- Author         : auto-generated by wbgen2 from wb_orbit_intlk_regs.wb
--- Created        : Mon Oct 25 13:33:06 2021
+-- Created        : Tue Sep 24 11:12:27 2024
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_orbit_intlk_regs.wb
@@ -311,7 +311,8 @@ begin
             rddata_reg(27) <= regs_i.sts_ang_smaller_any_i;
             rddata_reg(28) <= regs_i.sts_ang_smaller_i;
             rddata_reg(29) <= regs_i.sts_ang_smaller_ltc_i;
-            rddata_reg(31 downto 30) <= regs_i.sts_reserved_i;
+            rddata_reg(30) <= regs_i.sts_min_sum_bigger_i;
+            rddata_reg(31) <= regs_i.sts_reserved_i;
             ack_sreg(0) <= '1';
             ack_in_progress <= '1';
           when "0010" => 
@@ -526,6 +527,7 @@ begin
 -- Angular Smaller Any (X/Y)
 -- Angular Smaller
 -- Angular Smaller Latched
+-- Minimum sum threshold detection
 -- Reserved
 -- Minimum Sum Threshold
 -- asynchronous std_logic_vector register : Minimum Sum Threshold (type RW/RO, fs_clk_i <-> clk_sys_i)

diff --git a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.wb b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs.wb
@@ -360,12 +360,20 @@ peripheral {
        access_dev = WRITE_ONLY;
     };
 
+    field {
+       name = "Minimum sum threshold detection";
+       description = "'1' if the BPM amplitudes sums are bigger than the value specified in min_sum, '0' otherwise.";
+       prefix = "min_sum_bigger";
+       type = BIT;
+       access_bus = READ_ONLY;
+       access_dev = WRITE_ONLY;
+    };
+
     field {
        name = "Reserved";
        description = "Ignore on write, read as 0's";
        prefix = "reserved";
-       type = SLV;
-       size = 2;
+       type = BIT;
        access_bus = READ_ONLY;
        access_dev = WRITE_ONLY;
     };

diff --git a/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs_pkg.vhd b/hdl/modules/wb_orbit_intlk/wbgen/wb_orbit_intlk_regs_pkg.vhd
@@ -3,7 +3,7 @@
 ---------------------------------------------------------------------------------------
 -- File           : wb_orbit_intlk_regs_pkg.vhd
 -- Author         : auto-generated by wbgen2 from wb_orbit_intlk_regs.wb
--- Created        : Mon Oct 25 13:33:06 2021
+-- Created        : Tue Sep 24 11:12:27 2024
 -- Standard       : VHDL'87
 ---------------------------------------------------------------------------------------
 -- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE wb_orbit_intlk_regs.wb
@@ -51,7 +51,8 @@ package orbit_intlk_wbgen2_pkg is
     sts_ang_smaller_any_i                    : std_logic;
     sts_ang_smaller_i                        : std_logic;
     sts_ang_smaller_ltc_i                    : std_logic;
-    sts_reserved_i                           : std_logic_vector(1 downto 0);
+    sts_min_sum_bigger_i                     : std_logic;
+    sts_reserved_i                           : std_logic;
     trans_x_diff_i                           : std_logic_vector(31 downto 0);
     trans_y_diff_i                           : std_logic_vector(31 downto 0);
     ang_x_diff_i                             : std_logic_vector(31 downto 0);
@@ -90,7 +91,8 @@ package orbit_intlk_wbgen2_pkg is
     sts_ang_smaller_any_i => '0',
     sts_ang_smaller_i => '0',
     sts_ang_smaller_ltc_i => '0',
-    sts_reserved_i => (others => '0'),
+    sts_min_sum_bigger_i => '0',
+    sts_reserved_i => '0',
     trans_x_diff_i => (others => '0'),
     trans_y_diff_i => (others => '0'),
     ang_x_diff_i => (others => '0'),
@@ -221,6 +223,7 @@ package body orbit_intlk_wbgen2_pkg is
     tmp.sts_ang_smaller_any_i := f_x_to_zero(left.sts_ang_smaller_any_i) or f_x_to_zero(right.sts_ang_smaller_any_i);
     tmp.sts_ang_smaller_i := f_x_to_zero(left.sts_ang_smaller_i) or f_x_to_zero(right.sts_ang_smaller_i);
     tmp.sts_ang_smaller_ltc_i := f_x_to_zero(left.sts_ang_smaller_ltc_i) or f_x_to_zero(right.sts_ang_smaller_ltc_i);
+    tmp.sts_min_sum_bigger_i := f_x_to_zero(left.sts_min_sum_bigger_i) or f_x_to_zero(right.sts_min_sum_bigger_i);
     tmp.sts_reserved_i := f_x_to_zero(left.sts_reserved_i) or f_x_to_zero(right.sts_reserved_i);
     tmp.trans_x_diff_i := f_x_to_zero(left.trans_x_diff_i) or f_x_to_zero(right.trans_x_diff_i);
     tmp.trans_y_diff_i := f_x_to_zero(left.trans_y_diff_i) or f_x_to_zero(right.trans_y_diff_i);

diff --git a/hdl/sim/regs/wb_orbit_intlk_regs.vh b/hdl/sim/regs/wb_orbit_intlk_regs.vh
@@ -76,8 +76,10 @@
 `define ORBIT_INTLK_STS_ANG_SMALLER 32'h10000000
 `define ORBIT_INTLK_STS_ANG_SMALLER_LTC_OFFSET 29
 `define ORBIT_INTLK_STS_ANG_SMALLER_LTC 32'h20000000
-`define ORBIT_INTLK_STS_RESERVED_OFFSET 30
-`define ORBIT_INTLK_STS_RESERVED 32'hc0000000
+`define ORBIT_INTLK_STS_MIN_SUM_BIGGER_OFFSET 30
+`define ORBIT_INTLK_STS_MIN_SUM_BIGGER 32'h40000000
+`define ORBIT_INTLK_STS_RESERVED_OFFSET 31
+`define ORBIT_INTLK_STS_RESERVED 32'h80000000
 `define ADDR_ORBIT_INTLK_MIN_SUM       6'h8
 `define ADDR_ORBIT_INTLK_TRANS_MAX_X   6'hc
 `define ADDR_ORBIT_INTLK_TRANS_MAX_Y   6'h10