Merge branch 'devel'

hdl/syn/afc_v3/vivado/dbe_bpm2_bo_sirius/Manifest.py

@@ -0,0 +1,38 @@
+target = "xilinx"
+action = "synthesis"
+
+syn_device = "xc7a200t"
+syn_grade = "-2"
+syn_package = "ffg1156"
+syn_top = "dbe_bpm2"
+syn_project = "dbe_bpm2"
+syn_tool = "vivado"
+syn_properties = [
+    ["steps.synth_design.args.more options", "-verbose"],
+    ["steps.synth_design.args.retiming", "1"],
+    ["steps.synth_design.args.assert", "1"],
+    ["steps.opt_design.args.verbose", "1"],
+    ["steps.opt_design.args.directive", "Explore"],
+    ["steps.opt_design.is_enabled", "1"],
+    ["steps.place_design.args.directive", "Explore"],
+    ["steps.place_design.args.more options", "-verbose"],
+    ["steps.phys_opt_design.args.directive", "AlternateFlowWithRetiming"],
+    ["steps.phys_opt_design.args.more options", "-verbose"],
+    ["steps.phys_opt_design.is_enabled", "1"],
+    ["steps.route_design.args.directive", "Explore"],
+    ["steps.route_design.args.more options", "-verbose"],
+    ["steps.post_route_phys_opt_design.args.directive", "AddRetime"],
+    ["steps.post_route_phys_opt_design.args.more options", "-verbose"],
+    ["steps.post_route_phys_opt_design.is_enabled", "1"],
+    ["steps.write_bitstream.args.verbose", "1"]]
+
+import os
+import sys
+if os.path.isfile("synthesis_descriptor_pkg.vhd"):
+    files = ["synthesis_descriptor_pkg.vhd"];
+else:
+    sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)")
+
+machine_pkg = "sirius_bo_250M";
+
+modules = { "local" : [ "../../../../top/afc_v3/vivado/dbe_bpm2" ] };

hdl/syn/afc_v3/vivado/dbe_bpm2_bo_sirius/build_synthesis_sdb.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+# Exit on error
+set -e
+# Check for uninitialized variables
+set -u
+
+# Maximum of 16 chars
+SYNTH_INFO_PROJECT="bpm-gw-bo-sirius"
+SYNTH_INFO_TOOL="VIVADO"
+SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2)
+
+SYNTH_INFO_COMMAND="../../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}"
+
+# Generate synthesis file
+echo $SYNTH_INFO_COMMAND
+eval $SYNTH_INFO_COMMAND

hdl/syn/afc_v3/vivado/dbe_bpm2_sr_sirius/Manifest.py

@@ -0,0 +1,38 @@
+target = "xilinx"
+action = "synthesis"
+
+syn_device = "xc7a200t"
+syn_grade = "-2"
+syn_package = "ffg1156"
+syn_top = "dbe_bpm2"
+syn_project = "dbe_bpm2"
+syn_tool = "vivado"
+syn_properties = [
+    ["steps.synth_design.args.more options", "-verbose"],
+    ["steps.synth_design.args.retiming", "1"],
+    ["steps.synth_design.args.assert", "1"],
+    ["steps.opt_design.args.verbose", "1"],
+    ["steps.opt_design.args.directive", "Explore"],
+    ["steps.opt_design.is_enabled", "1"],
+    ["steps.place_design.args.directive", "Explore"],
+    ["steps.place_design.args.more options", "-verbose"],
+    ["steps.phys_opt_design.args.directive", "AlternateFlowWithRetiming"],
+    ["steps.phys_opt_design.args.more options", "-verbose"],
+    ["steps.phys_opt_design.is_enabled", "1"],
+    ["steps.route_design.args.directive", "Explore"],
+    ["steps.route_design.args.more options", "-verbose"],
+    ["steps.post_route_phys_opt_design.args.directive", "AddRetime"],
+    ["steps.post_route_phys_opt_design.args.more options", "-verbose"],
+    ["steps.post_route_phys_opt_design.is_enabled", "1"],
+    ["steps.write_bitstream.args.verbose", "1"]]
+
+import os
+import sys
+if os.path.isfile("synthesis_descriptor_pkg.vhd"):
+    files = ["synthesis_descriptor_pkg.vhd"];
+else:
+    sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)")
+
+machine_pkg = "sirius_sr_250M";
+
+modules = { "local" : [ "../../../../top/afc_v3/vivado/dbe_bpm2" ] };

hdl/syn/afc_v3/vivado/dbe_bpm2_sr_sirius/build_synthesis_sdb.sh

@@ -0,0 +1,17 @@
+#!/bin/bash
+
+# Exit on error
+set -e
+# Check for uninitialized variables
+set -u
+
+# Maximum of 16 chars
+SYNTH_INFO_PROJECT="bpm-gw-sr-sirius"
+SYNTH_INFO_TOOL="VIVADO"
+SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2)
+
+SYNTH_INFO_COMMAND="../../../gen_sdbsyn.py --project ${SYNTH_INFO_PROJECT} --tool ${SYNTH_INFO_TOOL} --ver ${SYNTH_INFO_VER}"
+
+# Generate synthesis file
+echo $SYNTH_INFO_COMMAND
+eval $SYNTH_INFO_COMMAND

hdl/syn/afc_v3/vivado/dbe_bpm2/Manifest.py → hdl/syn/afc_v3/vivado/dbe_bpm2_sr_uvx/Manifest.py

@@ -33,6 +33,6 @@
 else:
     sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)")
 
-machine_pkg = "uvx_250M";
+machine_pkg = "uvx_sr_250M";
 
 modules = { "local" : [ "../../../../top/afc_v3/vivado/dbe_bpm2" ] };

hdl/syn/afc_v3/vivado/dbe_bpm2_sr_uvx/build_bitstream_local.sh

@@ -0,0 +1,11 @@
+#!/bin/bash
+
+# Exit on error
+set -e
+# Check for uninitialized variables
+set -u
+
+COMMAND="(./build_synthesis_sdb.sh; hdlmake; time make; date) 2>&1 | tee make_output &"
+
+echo $COMMAND
+eval $COMMAND

hdl/syn/afc_v3/vivado/dbe_bpm2_sr_uvx/build_bitstream_remote.sh

@@ -0,0 +1,11 @@
+#!/bin/bash
+
+# Exit on error
+set -e
+# Check for uninitialized variables
+set -u
+
+COMMAND="(hdlmake; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &"
+
+echo $COMMAND
+eval $COMMAND

hdl/syn/afc_v3/vivado/dbe_bpm/build_synthesis_sdb.sh → hdl/syn/afc_v3/vivado/dbe_bpm2_sr_uvx/build_synthesis_sdb.sh

@@ -5,7 +5,8 @@ set -e
 # Check for uninitialized variables
 set -u
 
-SYNTH_INFO_PROJECT="bpm-gw"
+# Maximum of 16 chars
+SYNTH_INFO_PROJECT="bpm-gw-sr-uvx"
 SYNTH_INFO_TOOL="VIVADO"
 SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2)
 

hdl/syn/afc_v3/vivado/dbe_bpm2_sr_uvx/synthesis_descriptor_pkg.vhd

@@ -0,0 +1,6 @@
+-- This file will be overwritten prior to synthesis,
+-- by hdlmake "syn_pre_cmd" specified on top Manifest.py.
+--
+-- However, hdlmake requires all files to be present
+-- on parsing-time. So, fool the tool with this dummy
+-- file so we can bypass this requirement.

hdl/syn/afc_v3/vivado/dbe_bpm/Manifest.py → hdl/syn/afc_v3/vivado/dbe_bpm_sr_uvx/Manifest.py

@@ -33,6 +33,6 @@
 else:
     sys.exit("Generate the SDB descriptor before using HDLMake (./build_synthesis_sdb.sh)")
 
-machine_pkg = "uvx_130M"
+machine_pkg = "uvx_sr_130M"
 
 modules = { "local" : [ "../../../../top/afc_v3/vivado/dbe_bpm" ] };

hdl/syn/afc_v3/vivado/dbe_bpm_sr_uvx/build_bitstream_local.sh

@@ -0,0 +1,11 @@
+#!/bin/bash
+
+# Exit on error
+set -e
+# Check for uninitialized variables
+set -u
+
+COMMAND="(./build_synthesis_sdb.sh; hdlmake; time make; date) 2>&1 | tee make_output &"
+
+echo $COMMAND
+eval $COMMAND

hdl/syn/afc_v3/vivado/dbe_bpm_sr_uvx/build_bitstream_remote.sh

@@ -0,0 +1,11 @@
+#!/bin/bash
+
+# Exit on error
+set -e
+# Check for uninitialized variables
+set -u
+
+COMMAND="(hdlmake; make cleanremote; time make remote; make sync; date) 2>&1 | tee make_output &"
+
+echo $COMMAND
+eval $COMMAND

hdl/syn/afc_v3/vivado/dbe_bpm2/build_synthesis_sdb.sh → hdl/syn/afc_v3/vivado/dbe_bpm_sr_uvx/build_synthesis_sdb.sh

@@ -5,7 +5,8 @@ set -e
 # Check for uninitialized variables
 set -u
 
-SYNTH_INFO_PROJECT="bpm-gw"
+# Maximum of 16 chars
+SYNTH_INFO_PROJECT="bpm-gw-sr-uvx"
 SYNTH_INFO_TOOL="VIVADO"
 SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2)
 

hdl/syn/afc_v3/vivado/dbe_bpm_sr_uvx/synthesis_descriptor_pkg.vhd

@@ -0,0 +1,6 @@
+-- This file will be overwritten prior to synthesis,
+-- by hdlmake "syn_pre_cmd" specified on top Manifest.py.
+--
+-- However, hdlmake requires all files to be present
+-- on parsing-time. So, fool the tool with this dummy
+-- file so we can bypass this requirement.

hdl/syn/afc_v3/vivado/dbe_pbpm/build_synthesis_sdb.sh

@@ -5,7 +5,7 @@ set -e
 # Check for uninitialized variables
 set -u
 
-SYNTH_INFO_PROJECT="bpm-pbpm"
+SYNTH_INFO_PROJECT="pbpm-gw"
 SYNTH_INFO_TOOL="VIVADO"
 SYNTH_INFO_VER=$(vivado -version | head -n 1 | cut -d' ' -f2 | cut -d 'v' -f2)