[BOLT][RISCV] Fix AUIPC/JALR call rewriting - #216882
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R_RISCV_CALL and R_RISCV_CALL_PLT cover an AUIPC/JALR pair, but BOLT treated them as four-byte relocations and decoded only the AUIPC immediate. Read both instructions and combine their signed high and low immediates so relocated call targets retain the low 12 bits. LTO can also leave linker-resolved intra-section AUIPC/JALR calls without relocations. On RV64, recognize valid call and tail-call pairs during disassembly, reconstruct the target (including JALR target-bit clearing), and attach an exact entry-point symbol before function reordering. Preserve alternate link registers such as x5 when canonicalizing calls. Relocation-less recovery is deliberately limited to RV64. RV32 target calculation requires XLEN-wrapped address arithmetic and remains out of scope for this change. This follows the RISC-V Unprivileged ISA RV32I sections "Integer Computational Instructions" (AUIPC) and "Control Transfer Instructions" (JALR): https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html It also follows the RISC-V ELF psABI "Relocations" chapter, specifically "Procedure Calls", where R_RISCV_CALL and R_RISCV_CALL_PLT apply to the AUIPC/JALR pair: https://riscv-non-isa.github.io/riscv-elf-psabi-doc/#_relocations Tested with four focused RISC-V CoreTests and the full BOLT RISCV lit directory (39 passed). Assisted-by: Codex
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R_RISCV_CALL and R_RISCV_CALL_PLT cover an AUIPC/JALR pair, but BOLT treated them as four-byte relocations and decoded only the AUIPC immediate. Read both instructions and combine their signed high and low immediates so relocated call targets retain the low 12 bits.
LTO can also leave linker-resolved intra-section AUIPC/JALR calls without relocations. Recognize valid standard call and tail-call pairs during disassembly, reconstruct the target (including JALR target-bit clearing), and attach a symbol reference before function reordering.
This follows the RISC-V Unprivileged ISA RV32I sections "Integer Computational Instructions" (AUIPC) and "Control Transfer Instructions" (JALR): https://docs.riscv.org/reference/isa/v20260120/unpriv/rv32.html
It also follows the RISC-V ELF psABI "Relocations" chapter, specifically "Procedure Calls", where R_RISCV_CALL and R_RISCV_CALL_PLT apply to the AUIPC/JALR pair: https://riscv-non-isa.github.io/riscv-elf-psabi-doc/#_relocations
Tested with the focused RISC-V CoreTests and the full BOLT RISCV lit directory (38 passed).
Scope: Relocation-less AUIPC/JALR recovery is intentionally RV64-only. RV32 XLEN-wrapped target arithmetic is deferred to a follow-up.
Assisted-by: Codex