VerilogTests

A repository for some modules I made while learning Verilog. Each module comes with a test bench to check the module behaviour.

If using iverilog, compile with the -g2012 flag.

Name		Name	Last commit message	Last commit date
Latest commit History 13 Commits
.gitignore		.gitignore
README.md		README.md
counter.v		counter.v
counter_test.v		counter_test.v
dlatch.v		dlatch.v
dlatch8bit.v		dlatch8bit.v
dlatch8bit_test.v		dlatch8bit_test.v
dlatch_test.v		dlatch_test.v
full_adder.v		full_adder.v
half_adder.v		half_adder.v
left_shifter.v		left_shifter.v
lifo.v		lifo.v
lifo_test.v		lifo_test.v
mult2to1.v		mult2to1.v
mult2to1_test.v		mult2to1_test.v
right_shifter.v		right_shifter.v
ripple_adder.v		ripple_adder.v
ripple_adder_test.v		ripple_adder_test.v
tristate.v		tristate.v
tristate_test.v		tristate_test.v

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