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instruction_check: enhancement #405

Merged
merged 1 commit into from
Sep 29, 2024
Merged

instruction_check: enhancement #405

merged 1 commit into from
Sep 29, 2024

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haoliang-Zhu
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Depending on the platform, different test cases are executed now and some other optimizations to enhance the robustness of the code.

},
"PREFETCHI": {
"cpuid": ['7', '0', '1', '0', 'd', '14'],
"platforms": {"SPR", "EMR", "GNR"}
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I don't think SPR/EMR support PREFETCHI.

},
"FRED": {
"cpuid": ['7', '0', '1', '0', 'a', '17'],
"platforms": {}
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What does the empty of platforms mean? Seems FRED only be supported on CWF and DMR.

},
"AMX_FP16": {
"cpuid": ['7', '0', '1', '0', 'a', '21'],
"platforms": {"SPR", "EMR", "GNR"}
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Seems SPR/EMR doesn't support AMX_FP16.

Did you test your patch on these platform?

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Thank you for your suggestion. I previously conducted tests on SPR, GNR, and SRF, but there may be some errors. I will double-check.

1. Depending on the platform, different test cases are executed now.
2. Some other optimizations to enhance the robustness of the code.

Signed-off-by: Haoliang Zhu <[email protected]>
@ysun ysun merged commit 2e066ab into intel:main Sep 29, 2024
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3 participants