This project is tested and implemented in FPGA Altera DE2-115
-
Notifications
You must be signed in to change notification settings - Fork 0
hl271/uart_with_fifo
This commit does not belong to any branch on this repository, and may belong to a fork outside of the repository.
Folders and files
| Name | Name | Last commit message | Last commit date | |
|---|---|---|---|---|
Repository files navigation
About
Verilog implementation of UART protocol with integrated FIFO buffer
Topics
Resources
Stars
Watchers
Forks
Releases
No releases published
Packages 0
No packages published