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Feature: VLSIR-based Netlisting Support #51

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1 change: 1 addition & 0 deletions .pre-commit-config.yaml
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Original file line number Diff line number Diff line change
@@ -1,3 +1,4 @@
exclude: '\.(ngspice|xyce)$'
repos:
- repo: https://github.com/pre-commit/pre-commit-hooks
rev: v5.0.0
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9 changes: 6 additions & 3 deletions docs/_config.yml
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Expand Up @@ -4,26 +4,29 @@ title: gf180
author: gdsfactory
logo: logo.png
# Force re-execution of notebooks on each build.

# See https://jupyterbook.org/content/execute.html
execute:
execute_notebooks: cache
timeout: -1
allow_errors: true
# execute_notebooks: force
# execute_notebooks: "off"
# exclude_patterns:
# - '*notebooks/devsim/01_pin_waveguide*'
# execute_notebooks: "off"
# exclude_patterns:
# - '*notebooks/devsim/01_pin_waveguide*'
latex:
latex_engine: pdflatex # one of 'pdflatex', 'xelatex' (recommended for unicode), 'luatex', 'platex', 'uplatex'
use_jupyterbook_latex: true # use sphinx-jupyterbook-latex for pdf builds as default
# Add a bibtex file so that we can create citations

html:
home_page_in_navbar: true
use_edit_page_button: true
use_repository_button: true
use_issues_button: true
baseurl: https://github.com/gdsfactory/gf180
# Information about where the book exists on the web

repository:
url: https://github.com/gdsfactory/gf180
path_to_book: docs # Optional path to your book, relative to the repository root
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15 changes: 15 additions & 0 deletions gf180mcu/cells/cap_mim.py
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Expand Up @@ -153,6 +153,21 @@ def cap_mim(
port_type="electrical",
)

# VLSIR Simulation Metadata
c.info["vlsir"] = {
"spice_type": "SUBCKT",
"spice_lib": "mim_cap",
"port_order": ["1", "2"],
"port_map": {"top": "1", "bottom": "2"},
"params": {"c_length": lc, "c_width": wc},
}

# Choose correct SPICE model
if mim_option == "B":
c.info["vlsir"].update({"model": "mim_1p0fF"})
else:
c.info["vlsir"].update({"model": "mim_2p0fF"})

return c


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18 changes: 18 additions & 0 deletions gf180mcu/cells/cap_mos.py
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Expand Up @@ -5,6 +5,8 @@
from gf180mcu.cells.via_generator import via_generator, via_stack
from gf180mcu.layers import layer

# TODO: For SPICE modelling, we must deduced
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nitpick (typo): Incomplete TODO text is unclear and slightly confusing.

The phrase we must deduced seems truncated and ungrammatical, which obscures the intent of the TODO. Please rephrase to clearly state what must be deduced for SPICE modelling (e.g., model name, biasing, or parameter extraction).

Suggested change
# TODO: For SPICE modelling, we must deduced
# TODO: For SPICE modelling, we must deduce the appropriate SPICE model name
# and parameter set for this capacitor structure (e.g., geometry- and
# bias-dependent parameters), and associate them with this cell.



@gf.cell
def cap_mos_inst(
Expand Down Expand Up @@ -521,6 +523,22 @@ def cap_mos(
port_type="electrical",
)

# VLSIR Simulation Metadata
c.info["vlsir"] = {
"spice_type": "SUBCKT",
"spice_lib": "moscap",
"port_order": ["1", "2"],
"port_map": {"source_drain": "1", "gate": "2"},
"params": {"c_length": lc, "c_width": wc},
}

# Model chooser
prefix = "nmoscap" if "cap_nmos" in type else "pmoscap"
voltage = "3p3" if volt == "3.3V" else "6p0"
suffix = "_b" if "_b" in type else ""

c.info["vlsir"].update({"model": f"{prefix}_{voltage}{suffix}"})

return c


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67 changes: 67 additions & 0 deletions gf180mcu/cells/diode.py
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Expand Up @@ -328,6 +328,20 @@ def diode_nd2ps(
port_type="electrical",
)

# VLSIR Simulation Metadata
c.info["vlsir"] = {
"spice_type": "DIODE",
"spice_lib": "dio",
"port_order": ["anode", "cathode"],
"port_map": {},
"params": {"l": la, "w": wa},
}

if volt == "3.3V":
c.info["vlsir"].update({"model": "np_3p3"})
else:
c.info["vlsir"].update({"model": "np_6p0"})

return c


Expand Down Expand Up @@ -653,6 +667,19 @@ def diode_pd2nw(
port_type="electrical",
)

c.info["vlsir"] = {
"spice_type": "DIODE",
"spice_lib": "dio",
"port_order": ["anode", "cathode"],
"port_map": {},
"params": {"l": la, "w": wa},
}

if volt == "3.3V":
c.info["vlsir"].update({"model": "pn_3p3"})
else:
c.info["vlsir"].update({"model": "pn_6p0"})

return c


Expand Down Expand Up @@ -803,6 +830,19 @@ def diode_nw2ps(
port_type="electrical",
)

c.info["vlsir"] = {
"spice_type": "DIODE",
"spice_lib": "dio",
"port_order": ["anode", "cathode"],
"port_map": {},
"params": {"l": la, "w": wa},
}

if volt == "3.3V":
c.info["vlsir"].update({"model": "nwp_3p3"})
else:
c.info["vlsir"].update({"model": "nwp_6p0"})

return c


Expand Down Expand Up @@ -1129,6 +1169,15 @@ def diode_pw2dw(
port_type="electrical",
)

c.info["vlsir"] = {
"model": "dnwpw",
"spice_type": "DIODE",
"spice_lib": "dio",
"port_order": ["anode", "cathode"],
"port_map": {},
"params": {"l": la, "w": wa},
}

return c


Expand Down Expand Up @@ -1573,6 +1622,15 @@ def diode_dw2ps(
port_type="electrical",
)

c.info["vlsir"] = {
"model": "dnwps",
"spice_type": "DIODE",
"spice_lib": "dio",
"port_order": ["anode", "cathode"],
"port_map": {},
"params": {"l": la, "w": wa},
}

return c


Expand Down Expand Up @@ -1977,6 +2035,15 @@ def sc_anode_strap(size: Float2 = (0.1, 0.1)) -> gf.Component:
port_type="electrical",
)

c.info["vlsir"] = {
"model": "sc_diode",
"spice_type": "DIODE",
"spice_lib": "dio",
"port_order": ["anode", "cathode"],
"port_map": {},
"params": {"l": la, "w": wa, "m": m},
}

# creating layout and cell in klayout
return c

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46 changes: 46 additions & 0 deletions gf180mcu/cells/fet.py
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Original file line number Diff line number Diff line change
Expand Up @@ -594,6 +594,8 @@ def hv_gen(c, c_inst, volt, dg_encx: float = 0.1, dg_ency: float = 0.1) -> None:
v5x.xmin = dg.xmin
v5x.ymin = dg.ymin

# TODO: Implement/delete
raise NotImplementedError()
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issue (bug_risk): Unconditional NotImplementedError in hv_gen will break any existing callers.

This will cause any code calling hv_gen to fail at runtime, which is a breaking change if it’s part of the public PDK API or used by other cells. If you’re deprecating it, either remove all usages in this PR or guard the exception behind a flag/config so existing designs continue to run.

# return c


Expand Down Expand Up @@ -819,6 +821,8 @@ def bulk_gr_gen(
)
)

# TODO: Implement/delete
raise NotImplementedError()
# return c


Expand Down Expand Up @@ -1437,6 +1441,24 @@ def nfet(
)
)

# VLSIR Simulation Metadata

# Model selection

c.info["vlsir"] = {
"model": "nmos_3p3" if volt == "3.3V" else "nmos_6p0",
"spice_type": "MOS",
"spice_lib": "nmos_3p3_t" if volt == "3.3V" else "nmos_6p0_t",
"port_order": ["d", "g", "s", "b"],
"port_map": {}, # TODO: Add GDSF Ports
"params": {
"w": w_gate,
"l": l_gate,
"nf": nf,
"m": 1, # TODO: Mentioned in function docstring?
},
}

return c


Expand Down Expand Up @@ -1971,6 +1993,21 @@ def pfet(
# bulk guardring

c.add_port(name="s", port=sd_diff.ports["e1"])

c.info["vlsir"] = {
"model": "pmos_3p3" if volt == "3.3V" else "pmos_6p0",
"spice_type": "MOS",
"spice_lib": "pmos_3p3_t" if volt == "3.3V" else "pmos_6p0_t",
"port_order": ["d", "g", "s", "b"],
"port_map": {}, # TODO: Add GDSF Ports
"params": {
"w": w_gate,
"l": l_gate,
"nf": nf,
"m": 1, # TODO: Mentioned in function docstring?
},
}

return c


Expand Down Expand Up @@ -2570,6 +2607,15 @@ def nfet_06v0_nvt(
nat.xmin = dg.xmin
nat.ymin = dg.ymin

c.info["vlsir"] = {
"model": "nmos_6p0_nat",
"spice_type": "SUBCKT",
"spice_lib": "nmos_6p0_nat_t",
"port_order": ["d", "g", "s", "b"],
"port_map": {}, # TODO: Add GDSF Ports
"params": {"w": w_gate, "l": l_gate, "nf": nf},
}

return c


Expand Down
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