Add STM32WL3xx variants

data/header_map.yaml

@@ -194,3 +194,4 @@ STM32G4A1xx: STM32G4A1xx
 STM32GBK1CB: STM32GBK1CB
 STM32U5xx: STM32U5A5, STM32U5A9, STM32U535, STM32U545, STM32U575, STM32U585, STM32U595, STM32U599
 STM32WB0x: STM32WB05, STM32WB06, STM32WB07, STM32WB09
+STM32WL3xx: STM32WL30K8, STM32WL30KB, STM32WL31C8, STM32WL31CB, STM32WL31K8, STM32WL31KB, STM32WL33C8, STM32WL33CB, STM32WL33CC, STM32WL33K8, STM32WL33KB, STM32WL33KC

data/registers/comp_wl33.yaml

@@ -0,0 +1,54 @@
+block/COMP:
+  description: COMP address block description.
+  items:
+  - name: CSR
+    description: CSR register.
+    byte_offset: 0
+    fieldset: CSR
+fieldset/CSR:
+  description: CSR register.
+  fields:
+  - name: EN
+    description: 'EN: Comparator enable bit This bit is set and cleared by software (only if LOCK not set). It switches on Comparator. 0: Comparator switched OFF 1: Comparator switched ON.'
+    bit_offset: 0
+    bit_size: 1
+  - name: PWRMODE
+    description: 'PWRMODE[1:0]: Power Mode of the comparator These bits are set and cleared by software (only if LOCK not set). They control the power/speed of the Comparator. 00:High speed 01 or 10:Medium speed 11:Ultra low power.'
+    bit_offset: 2
+    bit_size: 2
+  - name: INMSEL
+    description: 'INMSEL: Comparator input minus selection bits These bits are set and cleared by software (only if LOCK not set). They select which input is connected to the input minus of comparator. 000: 1/4 VREFINT 001: 1/2 VREFINT 010: 3/4VREFINT 011: VREFINT 100: DAC OUT 101: PA13 110: PB0 111: PB3.'
+    bit_offset: 4
+    bit_size: 3
+  - name: INPSEL
+    description: 'INPSEL[1:0]: Comparator input plus selection bit This bit is set and cleared by software (only if LOCK not set). 00: PA14 01: PB1 1x: PB2.'
+    bit_offset: 7
+    bit_size: 2
+  - name: POLARITY
+    description: 'POLARITY: Comparator polarity selection bit This bit is set and cleared by software (only if LOCK not set). It inverts Comparator polarity. 0: Comparator output value not inverted 1: Comparator output value inverted.'
+    bit_offset: 15
+    bit_size: 1
+  - name: HYST
+    description: 'HYST[1:0]: Comparator hysteresis selection bits These bits are set and cleared by software (only if LOCK not set). They select the Hysteresis voltage of the comparator . 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis.'
+    bit_offset: 16
+    bit_size: 2
+  - name: BLANKING
+    description: 'BLANKING[2:0]: Comparator blanking source selection bits These bits select which timer output controls the comparator output blanking. 000: No blanking 001: TIM2 OC4 selected as blanking source 010: TIM16 OC1 selected as blanking source All other values: reserved.'
+    bit_offset: 18
+    bit_size: 3
+  - name: BRGEN
+    description: 'BRGEN: Scaler bridge enable This bit is set and cleared by software (only if LOCK not set). This bit enable the bridge of the scaler. 0: Scaler resistor bridge disable 1: Scaler resistor bridge enable If SCALEN is set and BRGEN is reset, BG voltage reference is available but not 1/4BGAP, 1/2BGAP, 3/4 BGAP. BGAP value is sent instead of 1/4BGAP, 1/2BGAP, 3/4 BGAP. If SCALEN and BRGEN are set, 1/4 BGAP 1/2BGAP 3/4BGAP and BGAP voltage references are available.'
+    bit_offset: 22
+    bit_size: 1
+  - name: SCALEN
+    description: 'SCALEN: Voltage scaler enable bit This bit is set and cleared by software. This bit enable the outputs of the VREFINT divider available on the minus input of the Comparator 0: scaler disable 1: scaler enable.'
+    bit_offset: 23
+    bit_size: 1
+  - name: VALUE
+    description: 'VALUE: Comparator output status bit This bit is read-only. It reflects the current comparator output taking into account POLARITY bit effect.'
+    bit_offset: 30
+    bit_size: 1
+  - name: LOCK
+    description: 'LOCK: COMP_CSR register lock bit This bit is set by software and cleared by a hardware system reset. It locks the whole content of the comparator control register, COMP1_CSR[31:0]. 0: COMP1_CSR[31:0] are read/write 1: COMP1_CSR[31:0] are read-only.'
+    bit_offset: 31
+    bit_size: 1

data/registers/dac_wl33.yaml

@@ -0,0 +1,99 @@
+block/DAC:
+  description: DAC address block description.
+  items:
+  - name: CR
+    description: CR register.
+    byte_offset: 0
+    fieldset: CR
+  - name: SWTRIGR
+    description: SWTRIGR register.
+    byte_offset: 4
+    fieldset: SWTRIGR
+  - name: DHR
+    description: DHR register.
+    byte_offset: 16
+    fieldset: DHR
+  - name: DOR
+    description: DOR register.
+    byte_offset: 44
+    access: Read
+    fieldset: DOR
+  - name: SR
+    description: SR register.
+    byte_offset: 52
+    fieldset: SR
+fieldset/CR:
+  description: CR register.
+  fields:
+  - name: EN
+    description: 'EN: DAC channel enable This bit is set and cleared by software to enable/disable DAC channel. 0: DAC channel disabled 1: DAC channel enabled.'
+    bit_offset: 0
+    bit_size: 1
+  - name: BON
+    description: 'BON: DAC channel output buffer enable. This bit is set and cleared by software to enable/disable DAC channel output buffer. 0: DAC channel output buffer disabled 1: DAC channel output buffer enabled.'
+    bit_offset: 1
+    bit_size: 1
+  - name: TEN
+    description: 'TEN: DAC channel trigger enable This bit is set and cleared by software to enable/disable DAC channel trigger. 0: DAC channel trigger disabled and data written into the DAC_DHR register are transferred one APB0 clock cycle later to the DAC_DOR register 1: DAC channel trigger enabled and data from the DAC_DHR register are transferred three APB0 clock cycles later to the DAC_DOR register Note: When software trigger is selected, the transfer from the DAC_DHR register to the DAC_DOR register takes only one APB0 clock cycle.'
+    bit_offset: 2
+    bit_size: 1
+  - name: TSEL
+    description: 'TSEL[2:0]: DAC channel trigger selection These bits select the external event used to trigger DAC channel. 000: Timer 16 TRGO event 001: PA8 pin event from SYSCFG 010 to 011: Reserved 111: Software trigger Only used if bit TEN = 1 (DAC channel trigger enabled).'
+    bit_offset: 3
+    bit_size: 3
+  - name: WAVE
+    description: 'WAVE[1:0]: DAC channel noise/triangle wave generation enable These bits are set and cleared by software. 00: wave generation disabled 01: Noise wave generation enabled 1x: Triangle wave generation enabled Note: Only used if bit TEN = 1 (DAC channel trigger enabled).'
+    bit_offset: 6
+    bit_size: 2
+  - name: MAMP
+    description: 'MAMP[3:0]: DAC channel mask amplitude selector These bits are written by software to select mask in wave generation mode or amplitude in triangle generation mode. 0000: Unmask bit0 of LFSR triangle amplitude equal to 1 0001: Unmask bits[1:0] of LFSR triangle amplitude equal to 3 0010: Unmask bits[2:0] of LFSR triangle amplitude equal to 7 0011: Unmask bits[3:0] of LFSR triangle amplitude equal to 15 0100: Unmask bits[4:0] of LFSR triangle amplitude equal to 31 greater than or equal to 0101: Unmask bits[5:0] of LFSR triangle amplitude equal to 63.'
+    bit_offset: 8
+    bit_size: 4
+  - name: DMAEN
+    description: 'DMAEN: DAC channel DMA enable This bit is set and cleared by software. 0: DAC channel DMA mode disabled 1: DAC channel DMA mode enabled.'
+    bit_offset: 12
+    bit_size: 1
+  - name: DMAUDRIE
+    description: 'DMAUDRIE: DAC channel DMA Underrun Interrupt enable This bit is set and cleared by software. 0: DAC channel DMA Underrun Interrupt disabled 1: DAC channel DMA Underrun Interrupt enabled.'
+    bit_offset: 13
+    bit_size: 1
+  - name: CMPEN
+    description: 'CMPEN: DAC channel output to COMP INMINUS enable. This bit is set and cleared by software. 0: DAC channel output to COMP INMINUS disabled 1: DAC channel output to COMP INMINUS enabled.'
+    bit_offset: 14
+    bit_size: 1
+  - name: VCMEN
+    description: 'VCMEN: DAC channel output to VCM BUFFER enable. This bit is set and cleared by software. 0: DAC channel output to VCM BUFFER disabled 1: DAC channel output to VCM BUFFER enabled.'
+    bit_offset: 15
+    bit_size: 1
+  - name: VCMON
+    description: 'VCMON: VCMBUFF power-up. This bit is set and cleared by software. 0: VCM BUFFER OFF 1: VCM BUFFER ON.'
+    bit_offset: 16
+    bit_size: 1
+fieldset/DHR:
+  description: DHR register.
+  fields:
+  - name: DACDHR
+    description: 'DACDHR[5:0]: DAC channel 6-bit data These bits are written by software which specifies 6-bit data for DAC channel.'
+    bit_offset: 0
+    bit_size: 6
+fieldset/DOR:
+  description: DOR register.
+  fields:
+  - name: DACDOR
+    description: 'DACDOR[5:0]: DAC channel data output These bits are read-only, they contain data output for DAC channel.'
+    bit_offset: 0
+    bit_size: 6
+fieldset/SR:
+  description: SR register.
+  fields:
+  - name: DMAUDR
+    description: 'DMAUDR: DAC channel DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred for DAC channel 1: DMA underrun error condition occurred for DAC channel (the currently selected trigger is driving DAC channel conversion at a frequency higher than the DMA service capability rate).'
+    bit_offset: 13
+    bit_size: 1
+fieldset/SWTRIGR:
+  description: SWTRIGR register.
+  fields:
+  - name: SWTRIG
+    description: 'SWTRIG: DAC channel software trigger This bit is set by software to enable/disable the software trigger. 0: Software trigger disabled 1: Software trigger enabled Note: This bit is cleared by hardware (one APB0 clock cycle later) once the DAC_DHR register value has been loaded into the DAC_DOR register.'
+    bit_offset: 0
+    bit_size: 1

data/registers/dbgmcu_wl3.yaml

@@ -0,0 +1,55 @@
+block/DBGMCU:
+  items:
+  - name: CR
+    description: CR register.
+    byte_offset: 0
+    fieldset: CR
+  - name: DBG_APB0_FZ
+    description: DBG_APB0_FZ register.
+    byte_offset: 4
+    fieldset: DBG_APB0_FZ
+  - name: DBG_APB1_FZ
+    description: DBG_APB1_FZ register.
+    byte_offset: 8
+    fieldset: DBG_APB1_FZ
+fieldset/CR:
+  description: CR register.
+  fields:
+  - name: DBG_SLEEP
+    description: 'Allow debug of the CPU in SLEEP mode - 0: Normal operation. All clocks will be disabled automatically in SLEEP mode - 1: Automatic clock stop disabled. All active CPU clocks and oscillators will continue to run during SLEEP mode, allowing full CPU debug capability. On exit from SLEEP mode, the clock settings will be set to the SLEEP mode exit state.'
+    bit_offset: 0
+    bit_size: 1
+  - name: DBG_STOP
+    description: 'Allow debug of the CPU in DEEPSTOP mode - 0: Normal operation. All clocks will be disabled automatically in STOP mode - 1: Automatic clock stop disabled. All active CPU clocks and oscillators will continue to run during STOP mode, allowing full CPU debug capability. On exit from STOP mode, the clock settings will be set to the STOP mode exit state.'
+    bit_offset: 1
+    bit_size: 1
+fieldset/DBG_APB0_FZ:
+  description: DBG_APB0_FZ register.
+  fields:
+  - name: DBG_TIM2_STOP
+    description: 'TIM2 stop in the CPU debug - 0: Normal operation. TIM2 continues to operate while the CPU is in debug mode - 1: Stop in debug. TIM2 is frozen while the CPU is in debug mode.'
+    bit_offset: 0
+    bit_size: 1
+  - name: DBG_TIM16_STOP
+    description: 'TIM16 stop in the CPU debug - 0: Normal operation. TIM16 continues to operate while the CPU is in debug mode - 1: Stop in debug. TIM16 is frozen while the CPU is in debug mode.'
+    bit_offset: 1
+    bit_size: 1
+  - name: DBG_RTC_STOP
+    description: 'RTC stop in CPU debug - 0: Normal operation. RTC continues to operate while the CPU is in debug mode - 1: Stop in debug. RTC is frozen while the CPU is in debug mode.'
+    bit_offset: 12
+    bit_size: 1
+  - name: DBG_IWDG_STOP
+    description: 'IWDG stop in the CPU debug - 0: Normal operation. IWDG continues to operate while the CPU is in debug mode - 1: Stop in debug. IWDG is frozen while the CPU is in debug mode.'
+    bit_offset: 14
+    bit_size: 1
+fieldset/DBG_APB1_FZ:
+  description: DBG_APB1_FZ register.
+  fields:
+  - name: DBG_I2C1_STOP
+    description: 'I2C1 SMBUS timeout stop in CPU debug - 0: Normal operation. I2C1 SMBUS timeout continues to operate while the CPU is in debug mode - 1: Stop in debug. I2C1 SMBUS timeou is frozen while the CPU is in debug mode.'
+    bit_offset: 21
+    bit_size: 1
+  - name: DBG_I2C2_STOP
+    description: 'I2C2 SMBUS timeout stop in CPU debug - 0: Normal operation. I2C2 SMBUS timeout continues to operate while the CPU is in debug mode - 1: Stop in debug. I2C2 SMBUS timeou is frozen while the CPU is in debug mode.'
+    bit_offset: 23
+    bit_size: 1

data/registers/dmamux_wl3.yaml

@@ -0,0 +1,91 @@
+block/DMAMUX:
+  description: DMAMUX address block description.
+  items:
+  - name: C0CR
+    description: CxCR register.
+    byte_offset: 0
+    fieldset: C0CR
+  - name: C1CR
+    description: CxCR register.
+    byte_offset: 4
+    fieldset: C1CR
+  - name: C2CR
+    description: CxCR register.
+    byte_offset: 8
+    fieldset: C2CR
+  - name: C3CR
+    description: CxCR register.
+    byte_offset: 12
+    fieldset: C3CR
+  - name: C4CR
+    description: CxCR register.
+    byte_offset: 16
+    fieldset: C4CR
+  - name: C5CR
+    description: CxCR register.
+    byte_offset: 20
+    fieldset: C5CR
+  - name: C6CR
+    description: CxCR register.
+    byte_offset: 24
+    fieldset: C6CR
+  - name: C7CR
+    description: CxCR register.
+    byte_offset: 28
+    fieldset: C7CR
+fieldset/C0CR:
+  description: CxCR register.
+  fields:
+  - name: DMAREQ_ID
+    description: 'DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources.'
+    bit_offset: 0
+    bit_size: 5
+fieldset/C1CR:
+  description: CxCR register.
+  fields:
+  - name: DMAREQ_ID
+    description: 'DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources.'
+    bit_offset: 0
+    bit_size: 5
+fieldset/C2CR:
+  description: CxCR register.
+  fields:
+  - name: DMAREQ_ID
+    description: 'DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources.'
+    bit_offset: 0
+    bit_size: 5
+fieldset/C3CR:
+  description: CxCR register.
+  fields:
+  - name: DMAREQ_ID
+    description: 'DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources.'
+    bit_offset: 0
+    bit_size: 5
+fieldset/C4CR:
+  description: CxCR register.
+  fields:
+  - name: DMAREQ_ID
+    description: 'DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources.'
+    bit_offset: 0
+    bit_size: 5
+fieldset/C5CR:
+  description: CxCR register.
+  fields:
+  - name: DMAREQ_ID
+    description: 'DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources.'
+    bit_offset: 0
+    bit_size: 5
+fieldset/C6CR:
+  description: CxCR register.
+  fields:
+  - name: DMAREQ_ID
+    description: 'DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources.'
+    bit_offset: 0
+    bit_size: 5
+fieldset/C7CR:
+  description: CxCR register.
+  fields:
+  - name: DMAREQ_ID
+    description: 'DMAREQ_ID[4:0]: DMA REQuest IDentification Selects the input DMA request. C.f. the DMAMUX table about assignments of multiplexer inputs to resources.'
+    bit_offset: 0
+    bit_size: 5