remove unnecessary newline

dsengupta0628 · dsengupta0628 · commit be4144832c87 · 2026-03-10T02:20:44.000Z
Signed-off-by: dsengupta0628 &lt;dsengupta@precisioninno.com&gt;
diff --git a/test/verilog_unconnected_hpin.v b/test/verilog_unconnected_hpin.v
@@ -22,6 +22,3 @@ module block2 (in, clk, out, out2);
    BUFx2_ASAP7_75t_R u2 (.A(r1q), .Y(out));
    BUFx2_ASAP7_75t_R u3 (.A(out), .Y(out2));
 endmodule // block2
-
-
-
