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dsengupta0628dsengupta0628
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rename tests
Signed-off-by: dsengupta0628 <dsengupta@precisioninno.com>
1 parent bf469f5 commit 13f722f

4 files changed

Lines changed: 2 additions & 2 deletions

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‎test/regression_vars.tcl‎

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@@ -166,7 +166,7 @@ record_public_tests {
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verilog_attribute
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verilog_specify
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verilog_write_escape
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verilog_unconnected_pin
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verilog_unconnected_hpin
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}
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define_test_group fast [group_tests all]

test/verilog_unconnected_pin.ok renamed to test/verilog_unconnected_hpin.ok

File renamed without changes.

test/verilog_unconnected_pin.tcl renamed to test/verilog_unconnected_hpin.tcl

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@@ -1,5 +1,5 @@
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read_liberty asap7_small.lib.gz
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read_verilog verilog_unconnected_pin.v
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read_verilog verilog_unconnected_hpin.v
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link_design top
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puts "Find b1/out2: [get_full_name [get_pins b1/out2]]"
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puts "Find b2/out2: [get_full_name [get_pins b2/out2]]"

test/verilog_unconnected_pin.v renamed to test/verilog_unconnected_hpin.v

File renamed without changes.

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